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PDF AS4C32M16SB-7TCN Data sheet ( Hoja de datos )
| Número de pieza | AS4C32M16SB-7TCN | |
| Descripción | CMOS synchronous 512Mb SDRAM | |
| Fabricantes | Alliance Semiconductor | |
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AS4C32M16SB-6TIN
AS4C32M16SB-7TIN
AS4C32M16SB-7TCN
Revision History
AS4C32M16SB-7TCN/AS4C32M16SB-7TIN/AS4C32M16SB-6TIN- 54pin TSOPII PACKAGE
Revision Details
Rev 1.0 Preliminary datasheet
Date
Jun 2016
Alliance Memory Inc. 511 Taylor Way, San Carlos, CA 94070 TEL: (650) 610-6800 FAX: (650) 620-9211
Alliance Memory Inc. reserves the right to change products or specification without notice
Confidential
- 1/55 -
Rev.1.0 June 2016
1 page  
AS4C32M16SB-6TIN
AS4C32M16SB-7TIN
AS4C32M16SB-7TCN
Pin Descriptions
Symbol
CLK
Type
Input
CKE
Input
BA0,BA1
Input
A0-A12
Input
CS#
Input
RAS#
Input
CAS#
Input
WE#
Input
LDQM,
UDQM
Input
Table 3. Pin Details
Description
Clock: CLK is driven by the system clock. All SDRAM input signals are sampled on
the positive edge of CLK. CLK also increments the internal burst counter and
controls the output registers.
Clock Enable: CKE activates (HIGH) and deactivates (LOW) the CLK signal. If
CKE goes low synchronously with clock (set-up and hold time same as other
inputs), the internal clock is suspended from the next clock cycle and the state of
output and burst address is frozen as long as the CKE remains low. When all banks
are in the idle state, deactivating the clock controls the entry to the Power Down and
Self Refresh modes. CKE is synchronous except after the device enters Power
Down and Self Refresh modes, where CKE becomes asynchronous until exiting the
same mode. The input buffers, including CLK, are disabled during Power Down and
Self Refresh modes, providing low standby power.
Bank Activate: BA0, BA1 input select the bank for operation.
BA1 BA0 Select Bank
0 0 BANK #A
0 1 BANK #B
1 0 BANK #C
1 1 BANK #D
Address Inputs: A0-A12 are sampled during the BankActivate command (row
address A0-A12) and Read/Write command (column address A0-A9 with A10
defining Auto Precharge) to select one location out of the 8M available in the
respective bank. During a Precharge command, A10 is sampled to determine if all
banks are to be precharged (A10 = HIGH). The address inputs also provide the
op-code during a Mode Register Set command.
Chip Select: CS# enables (sampled LOW) and disables (sampled HIGH) the
command decoder. All commands are masked when CS# is sampled HIGH. CS#
provides for external bank selection on systems with multiple banks. It is considered
part of the command code.
Row Address Strobe: The RAS# signal defines the operation commands in
conjunction with the CAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# and CS# are asserted "LOW" and CAS# is asserted "HIGH"
either the BankActivate command or the Precharge command is selected by the
WE# signal. When the WE# is asserted "HIGH" the BankActivate command is
selected and the bank designated by BA is turned on to the active state. When the
WE# is asserted "LOW" the Precharge command is selected and the bank
designated by BA is switched to the idle state after the precharge operation.
Column Address Strobe: The CAS# signal defines the operation commands in
conjunction with the RAS# and WE# signals and is latched at the positive edges of
CLK. When RAS# is held "HIGH" and CS# is asserted "LOW" the column access is
started by asserting CAS# "LOW". Then, the Read or Write command is selected by
asserting WE# "LOW" or "HIGH".
Write Enable: The WE# signal defines the operation commands in conjunction with
the RAS# and CAS# signals and is latched at the positive edges of CLK. The WE#
input is used to select the BankActivate or Precharge command and Read or Write
command.
Data Input/Output Mask: Controls output buffers in read mode and masks Input
data in write mode.
Confidential
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Rev.1.0 June 2016
5 Page 
AS4C32M16SB-6TIN
AS4C32M16SB-7TIN
AS4C32M16SB-7TCN
5 Read and AutoPrecharge command
(RAS# = "H", CAS# = "L", WE# = "H", BAs = Bank, A10 = "H", A0-A9 = Column Address)
The Read and AutoPrecharge command automatically performs the precharge operation after the
read operation. Once this command is given, any subsequent command cannot occur within a time
delay of {tRP(min.) + burst length}. At full-page burst, only the read operation is performed in this
command and the auto precharge function is ignored.
6 Write command
(RAS# = "H", CAS# = "L", WE# = "L", BAs = Bank, A10 = "L", A0-A9 = Column Address)
The Write command is used to write a burst of data on consecutive clock cycles from an active row
in an active bank. The bank must be active for at least tRCD(min.) before the Write command is issued.
During write bursts, the first valid data-in element will be registered coincident with the Write command.
Subsequent data elements will be registered on each successive positive clock edge (refer to the
following figure). The DQs remain with high-impedance at the end of the burst unless another
command is initiated. The burst length and burst sequence are determined by the mode register, which
is already programmed. A full-page burst will continue until terminated (at the end of the page it will
wrap to column 0 and continue).
CLK
COMMAND
DQ
T0 T1 T2 T3 T4 T5 T6 T7 T8
NOP
WRITE A
NOP
NOP
NOP
NOP
NOP
NOP
NOP
DIN A0
DIN A1
DIN A2
DIN A3
don’t care
The first data element and the write
are registered on the same clock edge
Figure 10. Burst Write Operation (Burst Length = 4)
A write burst without the auto precharge function may be interrupted by a subsequent Write,
BankPrecharge/PrechargeAll, or Read command before the end of the burst length. An interrupt
coming from Write command can occur on any clock cycle following the previous Write command (refer
to the following figure).
CLK
COMMAND
T0 T1 T2 T3 T4 T5 T6 T7 T8
NOP
WRITE A WRITE B
NOP
NOP
NOP
NOP
NOP
NOP
DQ
DIN A0
DIN B0
DIN B1
DIN B2
DIN B3
Figure 11. Write Interrupted by a Write (Burst Length = 4)
The Read command that interrupts a write burst without auto precharge function should be issued
one cycle after the clock edge in which the last data-in element is registered. In order to avoid data
contention, input data must be removed from the DQs at least one clock cycle before the first read data
appears on the outputs (refer to the following figure). Once the Read command is registered, the data
inputs will be ignored and writes will not be executed.
Confidential
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Rev.1.0 June 2016
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AS4C32M16SB-7TCN.PDF ] | |
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