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MT5VDDT872A の電気的特性と機能

MT5VDDT872AのメーカーはMicronです、この部品の機能は「64MB DDR SDRAM UDIMM」です。


製品の詳細 ( Datasheet PDF )

部品番号 MT5VDDT872A
部品説明 64MB DDR SDRAM UDIMM
メーカ Micron
ロゴ Micron ロゴ 




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MT5VDDT872A Datasheet, MT5VDDT872A PDF,ピン配置, 機能
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Features
DDR SDRAM UDIMM
MT5VDDT872A – 64MB1
MT5VDDT1672A – 128MB2
MT5VDDT3272A – 256MB2
For component data sheets, refer to Micron’s Web site: www.micron.com
Features
• 184-pin, unbuffered dual in-line memory module
(UDIMM)
• Fast data transfer rates: PC2100, PC2700, or PC3200
• 64MB (8 Meg x 72), 128MB (16 Meg x 72), and
256MB (32 Meg x 72)
• Supports ECC error detection and correction
• VDD = VDDQ = +2.5V
(-40B: VDD = VDDQ = +2.6V)
• VDDSPD = +2.3V to +3.6V
• 2.5V I/O (SSTL_2-compatible)
• Internal, pipelined double data rate (DDR)
2n-prefetch architecture
• Bidirectional data strobe (DQS) transmitted/
received with data—that is, source-synchronous
data capture
• Differential clock inputs (CK and CK#)
• Multiple internal device banks for concurrent
operation
• Single rank
• Selectable burst lengths (BL): 2, 4, or 8
• Auto precharge option
• Auto refresh and self refresh modes:
64MB = 15.625µs and 128MB, 256MB = 7.8125µs
maximum average periodic refresh interval
• Serial presence-detect (SPD) with EEPROM
• Selectable CAS latency (CL) for maximum
compatibility
• Gold edge contacts
Figure 1: 184-Pin UDIMM (MO-206 R/C C)
PCB height: 31.75mm (1.25in)
Options
• Operating temperature3
Commercial (0°C TA +70°C)
Industrial (–40°C TA +85°C)
• Package
184-pin DIMM (standard)
184-pin DIMM (Pb-free)
• Memory clock, speed, CAS latency
5.0ns (200 MHz), 400 MT/s, CL = 3.0
6.0ns (167 MHz), 333 MT/s, CL = 2.5
7.5ns (133 MHz), 266 MT/s, CL = 2.0
7.5ns (133 MHz), 266 MT/s, CL = 2.0
7.5ns (133 MHz), 266 MT/s, CL = 2.5
Marking
None
I
G
Y
-40B
-335
-262
-26A
-265
Notes: 1. End of life.
2. Not recommended for new designs.
3. Contact Micron for industrial temperature
module offerings.
Table 1: Key Timing Parameters
Speed
Grade
-40B
-335
-262
-26A
-265
Industry
Nomenclature
Data Rate (MT/s)
CL = 3 CL = 2.5 CL = 2
tRCD
(ns)
tRP
(ns)
tRC
(ns)
Notes
PC3200
PC2700
PC2100
PC2100
PC2100
400 333 266
15
15
55
333 266
18
18
60 1
266 266
15
15
60
266 266
20
20
65
266 200
20
20
65
Notes: 1. The values of tRCD and tRP for -335 modules show 18ns to align with industry specifications;
actual DDR SDRAM device specifications are 15ns.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
1 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.
Products and specifications discussed herein are subject to change by Micron without notice.

1 Page





MT5VDDT872A pdf, ピン配列
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
Pin Assignments and Descriptions
Pin Assignments and Descriptions
Table 6: Pin Assignments
184-Pin DDR UDIMM Front
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
1 VREF 24 DQ17 47 DQS8 70 VDD
2 DQ0 25 DQS2 48 A0 71 NC
3 VSS 26 VSS 49 CB2 72 DQ48
4 DQ1 27 A9 50 VSS 73 DQ49
5 DQS0 28 DQ18 51 CB3 74 VSS
6 DQ2 29 A7 52 BA1 75 CK2#
7 VDD 30 VDDQ 53 DQ32 76 CK2
8 DQ3 31 DQ19 54 VDDQ 77 VDDQ
9 NC 32 A5 55 DQ33 78 DQS6
10 NC 33 DQ24 56 DQS4 79 DQ50
11 VSS 34 VSS 57 DQ34 80 DQ51
12 DQ8 35 DQ25 58 VSS 81 VSS
13 DQ9 36 DQS3 59 BA0 82 NC
14 DQS1 37 A4 60 DQ35 83 DQ56
15 VDDQ 38 VDD 61 DQ40 84 DQ57
16 CK1 39 DQ26 62 VDDQ 85 VDD
17 CK1# 40 DQ27 63 WE# 86 DQS7
18 VSS 41 A2 64 DQ41 87 DQ58
19 DQ10 42 VSS 65 CAS# 88 DQ59
20 DQ11 43 A1 66 VSS 89 VSS
21 CKE0 44 CB0 67 DQS5 90 NC
22 VDDQ 45 CB1 68 DQ42 91 SDA
23 DQ16 46 VDD 69 DQ43 92 SCL
184-Pin DDR UDIMM Back
Pin Symbol Pin Symbol Pin Symbol Pin Symbol
93 VSS 116 VSS 139 VSS 162 DQ47
94 DQ4 117 DQ21 140 DM8/ 163 NC
DQS17
95 DQ5 118 A11 141 A10 164 VDDQ
96 VDDQ 119 DM2/ 142 CB6 165 DQ52
DQS11
97 DM0/ 120 VDD 143 VDDQ 166 DQ53
DQS9
98 DQ6 121 DQ22 144 CB7 167 NC
99 DQ7 122 A8 145 VSS 168 VDD
100 VSS 123 DQ23 146 DQ36 169 DM6/
DQS15
101 NC 124 VSS 147 DQ37 170 DQ54
102 NC 125 A6 148 VDD 171 DQ55
103 NC 126 DQ28 149 DM4/ 172 VDDQ
DQS13
104 VDDQ 127 DQ29 150 DQ38 173 NC
105 DQ12 128 VDDQ 151 DQ39 174 DQ60
106 DQ13 129 DM3/ 152 VSS 175 DQ61
DQS12
107 DM1/ 130 A3 153 DQ44 176 VSS
DQS10
108 VDD 131 DQ30 154 RAS# 177 DM7/
DQS16
109 DQ14 132 VSS 155 DQ45 178 DQ62
110 DQ15 133 DQ31 156 VDDQ 179 DQ63
111 NC 134 CB4 157 S0# 180 VDDQ
112 VDDQ 135 CB5 158 NC 181 SA0
113 NC 136 VDDQ 159 DM5/ 182 SA1
DQS14
114 DQ20 137 CK0 160 VSS 183 SA2
115 A12 138 CK0# 161 DQ46 184 VDDSPD
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
3 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.


3Pages


MT5VDDT872A 電子部品, 半導体
64MB, 128MB, 256MB (x72, ECC, SR) 184-Pin DDR SDRAM UDIMM
General Description
General Description
The MT5VDDT872A, MT5VDDT1672A, and MT5VDDT3272A are high-speed CMOS,
dynamic random access 64MB, 128MB, and 256MB memory modules organized in a x72
configuration. These modules use DDR SDRAM devices with four internal banks.
DDR SDRAM modules use a double data rate architecture to achieve high-speed opera-
tion. The double data rate architecture is essentially a 2n-prefetch architecture with an
interface designed to transfer two data words per clock cycle at the I/O pins. A single
read or write access for DDR SDRAM modules effectively consists of a single
2n-bit-wide, one-clock-cycle data transfer at the internal DRAM core and two corre-
sponding n-bit-wide, one-half-clock-cycle data transfers at the I/O pins.
A bidirectional data strobe (DQS) is transmitted externally, along with data, for use in
data capture at the receiver. DQS is a strobe transmitted by the DDR SDRAM during
READs and by the memory controller during WRITEs. DQS is edge-aligned with data for
READs and center-aligned with data for WRITEs.
DDR SDRAM modules operate from differential clock inputs (CK and CK#); the crossing
of CK going HIGH and CK# going LOW will be referred to as the positive edge of CK.
Commands are registered at every positive edge of CK. Input data is registered on both
edges of DQS, and output data is referenced to both edges of DQS, as well as to both
edges of CK.
Serial Presence-Detect Operation
DDR SDRAM modules incorporate serial presence-detect (SPD). The SPD function is
implemented using a 2,048-bit EEPROM. This nonvolatile storage device contains
256 bytes. The first 128 bytes are programmed by Micron to identify the module type and
various SDRAM organizations and timing parameters. The remaining 128 bytes of
storage are available for use by the customer. System READ/WRITE operations between
the master (system logic) and the slave EEPROM device (DIMM) occur via a standard I2C
bus using the DIMM’s SCL (clock) and SDA (data) signals, together with SA (2:0), which
provide eight unique DIMM/EEPROM addresses. Write protect (WP) is tied to VSS on the
module, permanently disabling hardware write protect.
PDF: 09005aef808143d9/Source: 09005aef806e1c40
DD5C8_16_32x72A.fm - Rev. F 10/07 EN
6 Micron Technology, Inc., reserves the right to change products or specifications without notice.
©2002 Micron Technology, Inc. All rights reserved.

6 Page



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部品番号部品説明メーカ
MT5VDDT872A

64MB DDR SDRAM UDIMM

Micron
Micron


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