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PDF NL10276BC30-38B Data sheet ( Hoja de datos )
| Número de pieza | NL10276BC30-38B | |
| Descripción | LCD Module | |
| Fabricantes | NEC | |
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TFT COLOR LCD MODULE
NL10276BC30-38B
38cm (15.0 Type)
XGA
LVDS interface (1port)
PRELIMINARY DATA SHEET
DOD-PP-1169 (2nd edition)
This PRELIMINARY DATA SHEET is updated
document from DOD-PP-1125(1).
All information is subject to change without notice.
Please confirm the sales representative before
starting to design your system.
Document Number: DOD-PP-1169 (2nd edition) 1 © NEC LCD Technologies, Ltd.
Published date: February 2011 CP(N)
2010-2011 All rights reserved.
1 page  
NL10276BC30-38B
2. GENERAL SPECIFICATIONS
Display area
Diagonal size of display
Drive system
Display color
Pixel
Pixel arrangement
Dot pitch
Pixel pitch
Module size
Weight
Contrast ratio
Viewing angle
Designed viewing direction
Polarizer surface
Polarizer pencil-hardness
Color gamut
304.128 (H) × 228.096 (V) mm
38cm (15.0 inches)
a-Si TFT active matrix
16,777,216 colors (6bit+FRC)
1,024 (H) × 768 (V) pixels
RGB (Red dot, Green dot, Blue dot) vertical stripe
0.099 (H) × 0.297 (V) mm
0.297 (H) × 0.297 (V) mm
326.5 (W) ×253.5 (H) × 11.7 (D) mm (typ.)
970g (typ.)
700:1 (typ.)
At the contrast ratio ≥ 10:1
• Horizontal: Right side 88° (typ.), Left side 88° (typ.)
• Vertical: Up side 88° (typ.), Down side 88° (typ.)
Viewing angle with optimum grayscale (γ≒2.2): Normal axis (perpendicular)
Antiglare
3H (min.) [by JIS K5600]
At LCD panel center
72% (typ.) [against NTSC color space]
Response time
Ton+Toff (10%←→ 90%)
25 ms (typ.)
Luminance
At IBL=7.5mArms / lamp
250 cd/m2 (typ.)
Signal system
LVDS 1port (Receiver: Equivalent of THC63LVDF84B, THine Electronics Inc.)
[8-bit digital signals for data of RGB colors, Dot clock (CLK),
Data enable (DE)]
Power supply voltage
LCD panel signal processing board: 3.3V
Edge light type: 2 cold cathode fluorescent lamps (without inverter)
Backlight
Replaceable part
• Lamp holder set: Type No.: 150LHS34
Recommended inverter (Option)
•Inverter: Type No.:150PW331
Power consumption
At IBL=7.5mArms / lamp, Checkered flag pattern
10.2 W (typ., Power dissipation of the inverter is not included.)
2
2
2
PRELIMINARY DATA SHEET DOD-PP-1169 (2nd edition)
5
5 Page 
NL10276BC30-38B
4.4 POWER SUPPLY VOLTAGE SEQUENCE
4.4.1 LCD panel signal processing board
VCC
Note1
0V
ON
3.0V
0.1ms < Tr < 80ms
OFF
2.5V 3.0V
20ms max.
ON
Toff > 200ms
Display signals*,
Function signals
Note2
0V
0.01ms < t < 50ms
VALID period
0.01ms < t < 50ms
* These signals should be measured at the terminal of 100Ω resistance.
Note1: If there is a voltage variation (voltage drop) at the rising edge of VCC below 3.0V, there is a
possibility that a product does not work due to a protection circuit.
Note2: Display signals (D0+/-, D1+/-, D2+/-, D3+/-, CLK+/-) and function signal (MSL) must be set
to Low or High impedance, except the VALID period (See above sequence diagram), in order
to avoid the circuitry damage.
If some of display and function signals of this product are cut while this product is working,
even if the signal input to it once again, it might not work normally. If a customer stops the
display and function signals, VCC also must be shut down.
The backlight should be turned on within the valid period of display and function signals, in
order to avoid unstable data display.
PRELIMINARY DATA SHEET DOD-PP-1169 (2nd edition)
11
11 Page | ||
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