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PDF HD64F3684G Data sheet ( Hoja de datos )
| Número de pieza | HD64F3684G | |
| Descripción | 16-Bit Single-Chip Microcomputer | |
| Fabricantes | Renesas | |
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The revision list summarizes the locations of
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be checked by referring to the relevant text.
16
H8/3687Group
Hardware Manual
Renesas 16-Bit Single-Chip
Microcomputer
H8 Family/H8/300H Tiny Series
H8/3687N HD64N3687G, HD6483687G,
H8/3687F HD64F3687, HD64F3687G,
H8/3687 HD6433687, HD6433687G,
H8/3686 HD6433686, HD6433686G,
H8/3685 HD6433685, HD6433685G,
H8/3684F HD64F3684, HD64F3684G,
H8/3684 HD6433684, HD6433684G,
H8/3683 HD6433683, HD6433683G,
H8/3682 HD6433682, HD6433682G
Rev.5.00 2005.11
1 page  
Configuration of This Manual
This manual comprises the following items:
1. General Precautions on Handling of Product
2. Configuration of This Manual
3. Preface
4. Contents
5. Overview
6. Description of Functional Modules
• CPU and System-Control Modules
• On-Chip Peripheral Modules
The configuration of the functional description of each module differs according to the
module. However, the generic style includes the following items:
i) Feature
ii) Input/Output Pin
iii) Register Description
iv) Operation
v) Usage Note
When designing an application system that includes this LSI, take notes into account. Each section
includes notes in relation to the descriptions given, and usage notes are given, as required, as the
final part of each section.
7. List of Registers
8. Electrical Characteristics
9. Appendix
10. Main Revisions and Additions in this Edition (only for revised versions)
The list of revisions is a summary of points that have been revised or added to earlier versions.
This does not include all of the revised contents. For details, see the actual locations in this
manual.
11. Index
Rev.5.00 Nov. 02, 2005 Page v of xxxii
5 Page 
3.2.5 Interrupt Flag Register 1 (IRR1)............................................................................. 53
3.2.6 Interrupt Flag Register 2 (IRR2)............................................................................. 55
3.2.7 Wakeup Interrupt Flag Register (IWPR) ................................................................ 55
3.3 Reset Exception Handling.................................................................................................... 57
3.4 Interrupt Exception Handling............................................................................................... 57
3.4.1 External Interrupts .................................................................................................. 57
3.4.2 Internal Interrupts ................................................................................................... 59
3.4.3 Interrupt Handling Sequence .................................................................................. 59
3.4.4 Interrupt Response Time......................................................................................... 60
3.5 Usage Notes ......................................................................................................................... 62
3.5.1 Interrupts after Reset............................................................................................... 62
3.5.2 Notes on Stack Area Use ........................................................................................ 62
3.5.3 Notes on Rewriting Port Mode Registers ............................................................... 62
Section 4 Address Break......................................................................................63
4.1 Register Descriptions ........................................................................................................... 63
4.1.1 Address Break Control Register (ABRKCR) ......................................................... 64
4.1.2 Address Break Status Register (ABRKSR) ............................................................ 65
4.1.3 Break Address Registers (BARH, BARL).............................................................. 65
4.1.4 Break Data Registers (BDRH, BDRL) ................................................................... 66
4.2 Operation ............................................................................................................................. 66
Section 5 Clock Pulse Generators........................................................................69
5.1 System Clock Generator ...................................................................................................... 70
5.1.1 Connecting Crystal Resonator ................................................................................ 70
5.1.2 Connecting Ceramic Resonator .............................................................................. 71
5.1.3 External Clock Input Method.................................................................................. 71
5.2 Subclock Generator.............................................................................................................. 72
5.2.1 Connecting 32.768-kHz Crystal Resonator............................................................. 72
5.2.2 Pin Connection when Not Using Subclock............................................................. 73
5.3 Prescalers ............................................................................................................................. 73
5.3.1 Prescaler S .............................................................................................................. 73
5.3.2 Prescaler W............................................................................................................. 73
5.4 Usage Notes ......................................................................................................................... 74
5.4.1 Note on Resonators................................................................................................. 74
5.4.2 Notes on Board Design ........................................................................................... 74
Section 6 Power-Down Modes ............................................................................75
6.1 Register Descriptions ........................................................................................................... 75
6.1.1 System Control Register 1 (SYSCR1) .................................................................... 76
Rev.5.00 Nov. 02, 2005 Page xi of xxxii
11 Page | ||
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