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PDF ATtiny13V Data sheet ( Hoja de datos )
| Número de pieza | ATtiny13V | |
| Descripción | 8-bit Microcontroller | |
| Fabricantes | ATMEL Corporation | |
| Logotipo |  |
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Features
• High Performance, Low Power AVR® 8-Bit Microcontroller
• Advanced RISC Architecture
– 120 Powerful Instructions – Most Single Clock Cycle Execution
– 32 x 8 General Purpose Working Registers
– Fully Static Operation
– Up to 20 MIPS Througput at 20 MHz
• High Endurance Non-volatile Memory segments
– 1K Bytes of In-System Self-programmable Flash program memory
– 64 Bytes EEPROM
– 64 Bytes Internal SRAM
– Write/Erase cyles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C (see page 6)
– Programming Lock for Self-Programming Flash & EEPROM Data Security
• Peripheral Features
– One 8-bit Timer/Counter with Prescaler and Two PWM Channels
– 4-channel, 10-bit ADC with Internal Voltage Reference
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
• Special Microcontroller Features
– debugWIRE On-chip Debug System
– In-System Programmable via SPI Port
– External and Internal Interrupt Sources
– Low Power Idle, ADC Noise Reduction, and Power-down Modes
– Enhanced Power-on Reset Circuit
– Programmable Brown-out Detection Circuit
– Internal Calibrated Oscillator
• I/O and Packages
– 8-pin PDIP/SOIC: Six Programmable I/O Lines
– 20-pad MLF: Six Programmable I/O Lines
• Operating Voltage:
– 1.8 - 5.5V for ATtiny13V
– 2.7 - 5.5V for ATtiny13
• Speed Grade
– ATtiny13V: 0 - 4 MHz @ 1.8 - 5.5V, 0 - 10 MHz @ 2.7 - 5.5V
– ATtiny13: 0 - 10 MHz @ 2.7 - 5.5V, 0 - 20 MHz @ 4.5 - 5.5V
• Industrial Temperature Range
• Low Power Consumption
– Active Mode:
• 1 MHz, 1.8V: 240 µA
– Power-down Mode:
• < 0.1 µA at 1.8V
8-bit
Microcontroller
with 1K Bytes
In-System
Programmable
Flash
ATtiny13
ATtiny13V
Rev. 2535J–AVR–08/10
1 page  
ATtiny13
The AVR core combines a rich instruction set with 32 general purpose working registers. All 32
registers are directly connected to the Arithmetic Logic Unit (ALU), allowing two independent
registers to be accessed in one single instruction executed in one clock cycle. The resulting
architecture is more code efficient while achieving throughputs up to ten times faster than con-
ventional CISC microcontrollers.
The ATtiny13 provides the following features: 1K byte of In-System Programmable Flash, 64
bytes EEPROM, 64 bytes SRAM, 6 general purpose I/O lines, 32 general purpose working reg-
isters, one 8-bit Timer/Counter with compare modes, Internal and External Interrupts, a 4-
channel, 10-bit ADC, a programmable Watchdog Timer with internal Oscillator, and three soft-
ware selectable power saving modes. The Idle mode stops the CPU while allowing the SRAM,
Timer/Counter, ADC, Analog Comparator, and Interrupt system to continue functioning. The
Power-down mode saves the register contents, disabling all chip functions until the next Inter-
rupt or Hardware Reset. The ADC Noise Reduction mode stops the CPU and all I/O modules
except ADC, to minimize switching noise during ADC conversions.
The device is manufactured using Atmel’s high density non-volatile memory technology. The
On-chip ISP Flash allows the Program memory to be re-programmed In-System through an SPI
serial interface, by a conventional non-volatile memory programmer or by an On-chip boot code
running on the AVR core.
The ATtiny13 AVR is supported with a full suite of program and system development tools
including: C Compilers, Macro Assemblers, Program Debugger/Simulators, and Evaluation kits.
2535J–AVR–08/10
5
5 Page 
Figure 4-3. The X-, Y-, and Z-registers
X-register
15
7
R27 (0x1B)
XH
ATtiny13
07
R26 (0x1A)
XL
0
0
Y-register
15
7
R29 (0x1D)
YH
07
R28 (0x1C)
YL
0
0
Z-register
15
7
R31 (0x1F)
ZH
0
7
R30 (0x1E)
ZL
0
0
In the different addressing modes these address registers have functions as fixed displacement,
automatic increment, and automatic decrement (see the instruction set reference for details).
4.5 Stack Pointer
The Stack is mainly used for storing temporary data, for storing local variables and for storing
return addresses after interrupts and subroutine calls. The Stack Pointer Register always points
to the top of the Stack. Note that the Stack is implemented as growing from higher memory loca-
tions to lower memory locations. This implies that a Stack PUSH command decreases the Stack
Pointer.
The Stack Pointer points to the data SRAM Stack area where the Subroutine and Interrupt
Stacks are located. This Stack space in the data SRAM is automaticall defined to the last
address in SRAM during power on reset. The Stack Pointer must be set to point above 0x60.
The Stack Pointer is decremented by one when data is pushed onto the Stack with the PUSH
instruction, and it is decremented by two when the return address is pushed onto the Stack with
subroutine call or interrupt. The Stack Pointer is incremented by one when data is popped from
the Stack with the POP instruction, and it is incremented by two when data is popped from the
Stack with return from subroutine RET or return from interrupt RETI.
The AVR Stack Pointer is implemented as two 8-bit registers in the I/O space. The number of
bits actually used is implementation dependent. Note that the data space in some implementa-
tions of the AVR architecture is so small that only SPL is needed. In this case, the SPH Register
will not be present.
4.5.1
SPL - Stack Pointer Low.
Bit
Read/Write
Initial Value
15
SP7
7
R/W
1
14
SP6
6
R/W
0
13
SP5
5
R/W
0
12
SP4
4
R/W
1
11
SP3
3
R/W
1
10
SP2
2
R/W
1
9
SP1
1
R/W
1
8
SP0
0
R/W
1
SPL
2535J–AVR–08/10
11
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