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PDF PIC24FJ32GA104 Data sheet ( Hoja de datos )
| Número de pieza | PIC24FJ32GA104 | |
| Descripción | 16-Bit General Purpose Flash Microcontrollers | |
| Fabricantes | Microchip | |
| Logotipo |  |
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PIC24FJ64GA104 Family
Data Sheet
28/44-Pin, 16-Bit General Purpose
Flash Microcontrollers
with nanoWatt XLP Technology
2010 Microchip Technology Inc.
DS39951C
1 page  
Pin Diagrams
28-Pin QFN(1,3)
PIC24FJ64GA104 FAMILY
PGED1/AN2/C2INB/RP0/CN4/RB0
PGEC1/AN3/C2INA/RP1/CN5/RB1
AN4/C1INB/SDA2/RP2/CN6/RB2
AN5/C1INA/SCL2/RP3/CN7/RB3
VSS
OSCI/CLKI/C1IND/CN30/RA2
OSCO/CLKO/CN29/PMA0/RA3
28 27 26 25 24 23 22
1 21
2 20
3
4
PIC24FJXXGA102
19
18
5 17
6 16
7 15
8 9 10 11 12 13 14
AN11/C1INC/RP13/CN13/PMRD/REFO/RB13
AN12/RP12/CN14/PMD0/RB12
PGEC2/TMS/RP11/CN15/PMD1/RB11
PGED2/TDI/RP10/CN16/PMD2/RB10
VCAP/VDDCORE
DISVREG
TDO/RP9/SDA1/CN21/PMD3/RB9
Legend:
Note 1:
2:
3:
RPn represents remappable peripheral pins.
Gray shading indicates 5.5V tolerant input pins.
Alternative multiplexing for SDA1 and SCL1 when the I2C1SEL bit is set.
The back pad on QFN devices should be connected to VSS.
2010 Microchip Technology Inc.
DS39951C-page 5
5 Page 
PIC24FJ64GA104 FAMILY
TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ64GA104 FAMILY
Features
PIC24FJ32GA102 PIC24FJ64GA102 PIC24FJ32GA104 PIC24FJ64GA104
Operating Frequency
DC – 32 MHz
Program Memory (bytes)
32K 64K 32K 64K
Program Memory (instructions)
11,008
22,016
11,008
22,016
Data Memory (bytes)
8,192
Interrupt Sources (soft vectors/
NMI traps)
45 (41/4)
I/O Ports
Ports A and B
Ports A, B, C
Total I/O Pins
21 35
Remappable Pins
16 26
Timers:
Total Number (16-bit)
5(1)
32-Bit (from paired 16-bit timers)
Input Capture Channels
Output Compare/PWM Channels
2
5(1)
5(1)
Input Change Notification Interrupt
21
31
Serial Communications:
UART
SPI (3-wire/4-wire)
I2C™
2(1)
2(1)
2
Parallel Communications (PMP/PSP)
Yes
JTAG Boundary Scan
Yes
10-Bit Analog-to-Digital Module
(input channels)
10
13
Analog Comparators
3
CTMU Interface
Yes
Resets (and delays)
POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode,
REPEAT Instruction, Hardware Traps, Configuration Word Mismatch
(PWRT, OST, PLL Lock)
Instruction Set
76 Base Instructions, Multiple Addressing Mode Variations
Packages
28-Pin QFN, SOIC, SSOP and SPDIP
44-Pin QFN and TQFP
Note 1: Peripherals are accessible through remappable pins.
2010 Microchip Technology Inc.
DS39951C-page 11
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet PIC24FJ32GA104.PDF ] | |
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