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GT24C128 の電気的特性と機能

GT24C128のメーカーはGiantec Semiconductorです、この部品の機能は「2-WIRE 128K Bits Serial EEPROM」です。


製品の詳細 ( Datasheet PDF )

部品番号 GT24C128
部品説明 2-WIRE 128K Bits Serial EEPROM
メーカ Giantec Semiconductor
ロゴ Giantec Semiconductor ロゴ 




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GT24C128 Datasheet, GT24C128 PDF,ピン配置, 機能
GT24C128
Advanced
GT24C128
2-WIRE 128K Bits
Serial EEPROM
(Not Recommended for New Design)
Copyright © 2011 Giantec Semiconductor Inc. (Giantec). All rights reserved. Giantec reserves the right to make changes to this specification and its products at any time without
notice. Giantec products are not designed, intended, authorized or warranted for use as components in systems or equipment intended for critical medical or surgical equipment,
aerospace or military, or other applications planned to support or sustain life. It is the customer's obligation to optimize the design in their own products for the best performance
and optimization on the functionality and etc. Giantec assumes no liability arising out of the application or use of any information, products or services described herein. Customers
are advised to obtain the latest version of this device specification before relying on any published information and prior placing orders for products.
Giantec Semiconductor, Inc.
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www.giantec-semi.com
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1 Page





GT24C128 pdf, ピン配列
GT24C128
1. Features
Two-Wire Serial Interface, I2CTM Compatible
Bi-directional data transfer protocol
Wide-voltage Operation
VCC = 1.8V to 5.5V
Speed: 400 KHz (1.8V) and 1 MHz (2.5V~5.5V)
Standby current (max.): 1 A, 1.8V
Operating current (max.): 2 mA, 1.8V
Hardware Data Protection
Write Protect Pin
Sequential & Random Read Features
Memory organization: 128Kb (16,384 x 8)
2. General Description
The GT24C128 is an industrial standard electrically
erasable programmable read only memory (EEPROM)
device that utilizes the industrial standard 2-wire interface
for communications. The GT24C128 contains a memory
array of 128K bits (16,384x8), which is organized in 64-byte
per page.
The EEPROM operates in a wide voltage range from 1.8V
to 5.5V, which fits most application. The product provides
low-power operations and low standby current. The device
is offered in Lead-free, RoHS, halogen free or Green
package. The available package types are 8-pin SOIC/SOP,
TSSOP and UDFN.
The GT24C128 is compatible to the standard 2-wire bus
protocol. The simple bus consists of Serial Clock (SCL) and
Serial Data (SDA) signals. Utilizing such bus protocol, a
Master device, such as a microcontroller, can usually
control one or more Slave devices, alike this GT24C128.
The bit stream over the SDA line includes a series of bytes,
which identifies a particular Slave device, an instruction, an
address within that Slave device, and a series of data, if
appropriate. The GT24C128 also has a Write Protect
Page Size: 64 bytes
Page write mode
Partial page writes allowed
Self timed write cycle: 5 ms (max.)
Noise immunity on inputs, besides Schmitt trigger
High-reliability
Endurance: 1 million cycles
Data retention: 100 years
Industrial grade
Packages: SOIC/SOP, TSSOP and UDFN
Lead-free, RoHS, Halogen free, Green
function via WP pin to cease from overwriting the data
stored inside the memory array.
In order to refrain the state machine entering into a wrong
state during power-up sequence or a power toggle off-on
condition, a power on reset circuit is embedded. During
power-up, the device does not respond to any instructions
until the supply voltage (VCC) has reached an acceptable
stable level above the reset threshold voltage. Once VCC
passes the power on reset threshold, the device is reset
and enters into the Standby mode. This would also avoid
any inadvertent Write operations during power-up stage.
During power-down process, the device will enter into
standby mode, once VCC drops below the power on reset
threshold voltage. In addition, the device will be in standby
mode after receiving the Stop command, provided that no
internal write operation is in progress. Nevertheless, it is not
recommended to send a command until the VCC reaches its
operating level.
Giantec Semiconductor, Inc.
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www.giantec-semi.com
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3Pages


GT24C128 電子部品, 半導体
GT24C128
5. Device Operation
The GT24C128 serial interface supports communications
using industrial standard 2-wire bus protocol, such as I2C.
5.1 2-WIRE Bus
The two-wire bus is defined as Serial Data (SDA), and
Serial Clock (SCL). The protocol defines any device that
sends data onto the SDA bus as a transmitter, and the
receiving devices as receivers. The bus is controlled by
Master device that generates the SCL, controls the bus
access, and generates the Start and Stop conditions. The
GT24C128 is the Slave device.
5.2 The Bus Protocol
Data transfer may be initiated only when the bus is not busy.
During a data transfer, the SDA line must remain stable
whenever the SCL line is high. Any changes in the SDA line
while the SCL line is high will be interpreted as a Start or
Stop condition.
The state of the SDA line represents valid data after a Start
condition. The SDA line must be stable for the duration of
the High period of the clock signal. The data on the SDA line
may be changed during the Low period of the clock signal.
There is one clock pulse per bit of data. Each data transfer
is initiated with a Start condition and terminated by a Stop
condition.
5.3 Start Condition
The Start condition precedes all commands to the device
and is defined as a High to Low transition of SDA when SCL
is High. The EEPROM monitors the SDA and SCL lines and
will not respond until the Start condition is met.
5.4 Stop Condition
The Stop condition is defined as a Low to High transition of
SDA when SCL is High. All operations must end with a Stop
condition.
5.5 Acknowledge
After a successful data transfer, each receiving device is
required to generate an ACK. The Acknowledging device
pulls down the SDA line.
5.6 Reset
The GT24C128 contains a reset function in case the 2-wire
bus transmission on is accidentally interrupted (e.g. a power
Giantec Semiconductor, Inc.
A1
loss), or needs to be terminated mid-stream. The reset is
initiated when the Master device creates a Start condition.
To do this, it may be necessary for the Master device to
monitor the SDA line while cycling the SCL up to nine times.
(For each clock signal transition to High, the Master checks
for a High level on SDA.)
5.7 Standby Mode
While in standby mode, the power consumption is minimal.
The GT24C128 enters into standby mode during one of the
following conditions: a) After Power-up, while no Op-code is
sent; b) After the completion of an operation and followed
by the Stop signal, provided that the previous operation is
not Write related; or c) After the completion of any internal
write operations.
5.8 Device Addressing
The Master begins a transmission on by sending a Start
condition, then sends the address of the particular Slave
devices to be communicated. The Slave device address is 8
bits format as shown in Figure. 5-5.
The four most significant bits of the Slave address are fixed
(1010) for GT24C128.
The next three bits, A0, A1 and A2, of the Slave address are
specifically related to EEPROM. Up to eight GT24C128
units can be connected to the 2-wire bus.
The last bit of the Slave address specifies whether a Read
or Write operation is to be performed. When this bit is set to
1, Read operation is selected. While it is set to 0, Write
operation is selected.
After the Master transmits the Start condition and Slave
address byte appropriately, the associated 2-wire Slave
device, GT24C128, will respond with ACK on the SDA line.
Then GT24C128 will pull down the SDA on the ninth clock
cycle, signaling that it received the eight bits of data.
The GT24C128 then prepares for a Read or Write operation
by monitoring the bus.
5.9 Write Operation
5.9.1 Byte Write
In the Byte Write mode, the Master device sends the Start
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部品番号部品説明メーカ
GT24C128

2-WIRE 128K Bits Serial EEPROM

Giantec Semiconductor
Giantec Semiconductor


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