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HS-1825AEH の電気的特性と機能

HS-1825AEHのメーカーはIntersilです、この部品の機能は「Radiation Hardened High-Speed Dual Output PWM」です。


製品の詳細 ( Datasheet PDF )

部品番号 HS-1825AEH
部品説明 Radiation Hardened High-Speed Dual Output PWM
メーカ Intersil
ロゴ Intersil ロゴ 




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HS-1825AEH Datasheet, HS-1825AEH PDF,ピン配置, 機能
DATASHEET
Radiation Hardened High-Speed, Dual Output PWM
HS-1825ARH, HS-1825AEH
The radiation hardened HS-1825ARH, HS-1825AEH pulse
width modulator is designed to be used in high frequency
switched-mode power supplies and can be used in either
current-mode or voltage-mode. It is well suited for single-ended
boost converter applications.
Device features include a precision voltage reference, low
power start-up circuit, high frequency oscillator, wide-band
error amplifier and fast current-limit comparator. The use of
proprietary process capabilities and unique design techniques
results in fast propagation delay times and high output current
over a wide range of output voltages.
Constructed with the Intersil radiation hardened Silicon Gate
(RSG) Dielectric Isolation BiCMOS process, the HS-1825ARH,
HS-1825AEH have been specifically designed to provide highly
reliable performance when exposed to harsh radiation
environments.
Features
• Electrically screened to DLA SMD # 5962-99558
• QML qualified per MIL-PRF-38535 Requirements
• Radiation environment
- Maximum total dose . . . . . . . . . . . . . . . . . . . . 300 krad(SI)
- Vertical architecture provides low dose rate immunity
- DI RSG process provides latch-up immunity
• Low start-up current. . . . . . . . . . . . . . . . . . . . . 100µA (Typical)
• Fast propagation delay . . . . . . . . . . . . . . . . . . . . 80ns (Typical)
• 12V to 30V operation
• 1A (peak) dual output drive capability
• 5.1V reference
• Undervoltage lockout
• Programmable soft-start
• Switching frequencies to 500kHz
• Latched overcurrent comparator with full cycle restart
• Programmable leading edge blanking circuit
Applications
• Current or voltage mode switching power supplies
• Motor speed and direction control
Pin Configuration
HS-1825ARH, HS-1825AEH
SBDIP (CDIP2-T16) AND FLATPACK (CDFP4-F16)
TOP VIEW
INV 1
NON-INV 2
E/A OUT 3
CLOCK 4
RT 5
CT 6
RAMP 7
SOFT START 8
16 VREF 5.1V
15 VCC
14 OUTPUT B
13 VC
12 POWER GND
11 OUTPUT A
10 GND
9 ILIM/SD
NOTE: Grounding the soft-start pin does not inhibit the outputs. The outputs may be inhibited by applying >1.26V to the ILIM/SD pin.
August 5, 2016
FN4561.10
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2002, 2005, 2008, 2012, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





HS-1825AEH pdf, ピン配列
HS-1825ARH, HS-1825AEH
Die Characteristics
DIE DIMENSIONS
4860µm x 3410µm (185 mils x 140 mils)
Thickness: 483µm ±25.4µm (19 mils ±1 mil)
INTERFACE MATERIALS
Glassivation
Type: PSG (Phosphorous Silicon Glass)
Thickness: 8.0kÅ ±1.0kÅ
Top Metallization
Type: ALSiCu
Thickness: 16.0kÅ 2kÅ
Substrate
Radiation Hardened Silicon Gate,
Dielectric Isolation
Backside Finish
Silicon
ASSEMBLY RELATED INFORMATION
Substrate Potential
Unbiased (DI)
ADDITIONAL INFORMATION
Worst Case Current Density
<2.0 x 105 A/cm2
Transistor Count
225
Metallization Mask Layout
HS-1825ARH, HS-1825AEH
RT
CT
RAMP
SS
ILIM
K^GND
(Note 3)
GND
CLK/LEB
EAOUT
IN+
IN-
VREF
VCC
OUTA
PGND
(Note 4)
(NoVtCe 4)
NOTES:
3. This is the oscillator ground (OSCGND) bond pad and must be
connected to GND.
4. PGND and VC each require two bond pad connections.
OUTB
(NPoGNteD 4)
VC
(Note 4)
Submit Document Feedback
3
FN4561.10
August 5, 2016


3Pages


HS-1825AEH 電子部品, 半導体
HS-1825ARH, HS-1825AEH
Package Outline Drawing
K16.A
16 LEAD CERAMIC METAL SEAL FLATPACK PACKAGE
Rev 2, 1/10
0.015 (0.38)
0.008 (0.20)
PIN NO. 1
ID OPTIONAL
1
2
0.050 (1.27 BSC)
PIN NO. 1
ID AREA
0.440 (11.18)
MAX
0.005 (0.13)
MIN
4
0.022 (0.56)
0.015 (0.38)
TOP VIEW
0.115 (2.92)
0.045 (1.14)
0.045 (1.14)
0.026 (0.66) 6
-C-
SEATING AND
BASE PLANE
0.285 (7.24)
0.245 (6.22)
0.13 (3.30)
MIN
LEAD FINISH
SIDE VIEW
0.009 (0.23)
0.004 (0.10)
-D-
0.370 (9.40)
0.250 (6.35)
0.03 (0.76) MIN
-H-
0.006 (0.15) LEAD FINISH
0.004 (0.10)
BASE
METAL
0.009 (0.23)
0.004 (0.10)
0.019 (0.48)
0.015 (0.38)
0.0015 (0.04)
MAX
0.022 (0.56)
0.015 (0.38)
SECTION A-A
3
NOTES:
1. Index area: A notch or a pin one identification mark shall be located
adjacent to pin one and shall be located within the shaded area shown.
The manufacturer’s identification shall not be used as a pin one
identification mark. Alternately, a tab may be used to identify pin one.
2. If a pin one identification mark is used in addition to a tab, the limits
of the tab dimension do not apply.
3. The maximum limits of lead dimensions (section A-A) shall be
measured at the centroid of the finished lead surfaces, when solder
dip or tin plate lead finish is applied.
4. Measure dimension at all four corners.
5. For bottom-brazed lead packages, no organic or polymeric materials
shall be molded to the bottom of the package to cover the leads.
6. Dimension shall be measured at the point of exit (beyond the
meniscus) of the lead from the body. Dimension minimum shall
be reduced by 0.0015 inch (0.038mm) maximum when solder dip
lead finish is applied.
7. Dimensioning and tolerancing per ANSI Y14.5M - 1982.
8. Controlling dimension: INCH.
Submit Document Feedback
6
FN4561.10
August 5, 2016

6 Page



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部品番号部品説明メーカ
HS-1825AEH

Radiation Hardened High-Speed Dual Output PWM

Intersil
Intersil


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