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PDF ISL29033 Data sheet ( Hoja de datos )
| Número de pieza | ISL29033 | |
| Descripción | Integrated Digital Ambient Light Sensor | |
| Fabricantes | Intersil | |
| Logotipo |  |
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DATASHEET
Ultra-Low Lux, Low Power, Integrated Digital Ambient
Light Sensor with Interrupt Function
ISL29033
The ISL29033 is an integrated ambient and infrared
light-to-digital converter with I2C (SMBus Compatible)
interface. Its advanced, self-calibrated photodiode array
emulates human eye response with excellent IR rejection. The
on-chip 16-bit ADC is capable of rejecting 50Hz and 60Hz
flicker caused by artificial light sources. The lux range select
feature allows users to program the lux range for optimized
counts/lux. Power consumption can be reduced to less than
0.3µA when powered down.
The ISL29033 supports a software and hardware interrupt that
remains asserted until the host clears it through the I2C
interface. The function of ADC conversion continues without
stopping after interrupt is asserted.
Designed to operate on supplies from 2.25V to 3.63V with an
I2C supply from 1.7V to 3.63V, the ISL29033 is specified for
operation across the -40°C to +85°C ambient temperature
range.
Related Literature
• For a full list of related documents, visit our web page
- ISL29033 product page
Features
• Ambient light sensing
• Simple output code directly proportional to lux
• Variable conversion resolution up to 16 bits
• Adjustable sensitivity up to 520 counts per lux
• Measurement range: 0.0019 to 8,000lux with four
selectable ranges
• Program interrupt feature
• Light sensor close to human eye response
- Excellent light sensor IR and UV rejection
• 75μA maximum operating current
- 0.3μA maximum shutdown current
• 6 Ld 2.0mmx2.1mmx0.7mm ODFN package
Applications
• Display and keypad dimming adjustment for:
- Mobile devices: smart phone, PDA, GPS
- Computing devices: notebook PC, webpad
- Consumer devices: LCD-TV, digital picture frame, digital
camera
• Industrial and medical light sensing
VDD
1
PHOTODIODE
ARRAY
LIGHT
DATA
PROCESS
INTEGRATION
ADC
IREF
fOSC
COMMAND
REGISTER
DATA
REGISTER
I2C/SMBus
INTERRUPT
REGISTER
5 SCL
6 SDA
3
REXT
2
GND
FIGURE 1. BLOCK DIAGRAM
4
INT
September 28, 2016
FN7656.5
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013, 2015, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL29033
I2C Electrical Specifications For SCL and SDA (Figure 2), unless otherwise noted, VDD = 3V, TA = +25°C, REXT = 499kΩ 1% and 1MΩ
1% tolerance.
PARAMETER
VI2C
fSCL
VIL
VIH
Vhys
VOL
DESCRIPTION
Supply Voltage Range for I2C Interface
SCL Clock Frequency
SCL and SDA Input Low Voltage
SCL and SDA Input High Voltage
Hysteresis of Schmitt Trigger Input
Low-Level Output Voltage (Open-Drain) at 4mA
Sink Current
TEST CONDITIONS
MIN
(Note 6)
1.7
1.25
0.05VDD
MAX
TYP (Note 6) UNIT
3.63
V
400 kHz
0.55
V
V
V
0.4 V
Ii Input Leakage for each SDA, SCL Pin
tSP Pulse Width of Spikes that must be Suppressed by
the Input Filter
-10 10 µA
50 ns
tAA
Ci
tHD:STA
SCL Falling Edge to SDA Output Data Valid
Capacitance for each SDA and SCL Pin
Hold Time (Repeated) START Condition
After this period, the first clock pulse
is generated.
600
900 ns
10 pF
ns
tLOW
tHIGH
tSU:STA
tHD:DAT
tSU:DAT
tR
tF
tSU:STO
tBUF
LOW Period of the SCL Clock
HIGH Period of the SCL Clock
Set-up Time for a Repeated START Condition
Data Hold Time
Data Set-Up Time
Rise Time of Both SDA and SCL Signals
Fall Time of Both SDA and SCL Signals
Set-Up Time for STOP Condition
Bus Free Time Between a STOP and START
Condition
Measured at the 30% of VDD crossing
1300
600
600
30
100
(Note 9)
(Note 9)
20 + 0.1xCb
20 + 0.1xCb
600
1300
ns
ns
ns
ns
ns
ns
ns
ns
ns
Cb Capacitive Load for Each Bus Line
400 pF
Rpull-up
SDA and SCL System Bus Pull-Up Resistor
Maximum is determined by tR and tF
1
kΩ
tVD;DAT
Data Valid Time
0.9 µs
tVD:ACK
Data Valid Acknowledge Time
0.9 µs
VnL Noise Margin at the LOW Level
0.1VDD
V
VnH Noise Margin at the HIGH Level
0.2VDD
V
NOTE:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization, and/or design.
7. A 550nm green LED is used in production test. The 550nm LED irradiance is calibrated to produce the same DATA count as a fluorescent light with
illuminance at the stated lux.
8. An 850nm IR LED is used in production test. The 850nm LED irradiance is calibrated to produce the same DATA_IR count as solar light with
illuminance at the stated lux.
9. Cb is the capacitance of the bus in pF.
Submit Document Feedback
5
FN7656.5
September 28, 2016
5 Page 
ISL29033
16
2
0.40
3
0.37
5
0.54
4
FIGURE 6. 6 LD ODFN SENSOR LOCATION OUTLINE
Submit Document Feedback 11
FN7656.5
September 28, 2016
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| PDF Descargar | [ Datasheet ISL29033.PDF ] | |
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