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PDF ISL267817 Data sheet ( Hoja de datos )
| Número de pieza | ISL267817 | |
| Descripción | 12-Bit Differential Input 200kSPS SAR ADC | |
| Fabricantes | Intersil | |
| Logotipo |  |
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12-Bit Differential Input 200kSPS SAR ADC
ISL267817
The ISL267817 is a 12-bit, 200kSPS sampling SAR-type ADC
which features excellent linearity over supply and temperature
variations, and provides a drop-in compatible alternative to all
ADS7817 performance grades. The robust, fully-differential
input offers high impedance to minimize errors due to leakage
currents, and the specified measurement accuracy is
maintained with input signals up to the supply rails.
The reference accepts inputs between 0.1V to 2.5V, providing
design flexibility in a wide variety of applications. The
ISL267817 also features up to 8kV Human Body Model ESD
survivability.
The serial digital interface is SPI compatible and is easily
interfaced to popular FPGAs and microcontrollers. Operating
from a 5V supply, power dissipation is 2.15mW at a sampling
rate of 200kSPS, and just 25µW between conversions utilizing
the Auto Power-Down mode, making the ISL267817 an
excellent solution for remote industrial sensors and
battery-powered instruments. It is available in the compact,
industry-standard 8 Lead SOIC and MSOP packages and is
specified for operation over the industrial temperature range
(-40°C to +85°C).
Features
• Drop-In Compatible with ADS7817 (All Performance Grades)
• Differential Input
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 200kHz Sampling Rate
• +4.75V to +5.25V Supply
• Low 2.15mW Operating Power (200kSPS)
• Power-down Current between Conversions: 3µA
• Excellent Differential Non-Linearity (1.0LSB max)
• Low THD: -85dB (typ)
• Pb-Free (RoHS Compliant)
• Available in SOIC and MSOP Packages
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
VREF
+VCC
+IN DCLOCK
–IN
SAR
LOGIC
SERIAL
INTERFACE
DOUT
CS/SHDN
VREF
GND
FIGURE 1. BLOCK DIAGRAM
1.00
0.75
0.50
0.25
0.00
-0.25
-0.50
-0.75
-1.00
0 512 1024 1536 2048 2560 3072 3584 4096
FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE
April 19, 2012
FN7877.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011, 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL267817
Electrical Specifications +VCC = +5V, fDCLOCK = 3.2MHz, fS = 200kSPS, VREF = 2.5V; VCM = VREF, Typical values are at TA = +25°C.
Boldface limits apply over the operating temperature range, -40°C to +85°C. (Continued)
SYMBOL
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6)
UNITS
REFERENCE INPUT
VREF VREF Input Range
0.1 2.5 V
VREFLEAK Current Drain
-100 4
100
µA
fSAMPLE = 12.5kHz
CS/SHDN = +VCC
-20 0.23
-3 0.01
20
3
µA
µA
DIGITAL INPUT/OUTPUT
Logic Family
CMOS
VIH Input High Voltage
VIL Input Low Voltage
VOH Output High Voltage
VOL Output Low Voltage
Output Coding
IOH = –250µA
IOL = 250µA
3
+VCC + 0.3
V
-0.3 0.8 V
3.5 V
0.4 V
Two’s Complement
ILEAK Input Leakage Current
CIN Input Capacitance
IOZ Floating-State Output Current
COUT Floating-State Output Capacitance
POWER REQUIREMENTS
-1
10
-1
5
1
1
µA
pF
µA
pF
VCC Supply Voltage Range
ICC Supply Current
Power Down Current
TEMPERATURE RANGE
fSAMPLE = 12.5kHz (Notes 8, 9)
fSAMPLE = 12.5kHz (Note 9)
CS/SHDN = +VCC, fSAMPLE = 0Hz
4.75
430
38
223
0.5
5.25
800
3
V
µA
µA
µA
µA
Specified Performance
-40 +85 °C
NOTES:
6. Compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design.
7. The absolute voltage applied to each analog input must be between GND and +VCC to guarantee datasheet performance.
8. fDCLOCK = 3.2MHz, CS/SHDN = +VCC for 241 clock cycles out of every 256.
9. See “Power vs Throughput Rate” on page 13 for more information regarding lower sample rates.
Timing Specifications Limits established by characterization and are not production tested. +VCC = 5V, fDCLOCK = 3.2MHz, fS = 200kSPS,
VREF = 2.5V; VCM = VREF. Boldface limits apply over the operating temperature range, -40°C to +85°C.
SYMBOL
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6) UNITS
tSMPL
tCONV
fCYC
tCSD
tSUCS
thDO
Analog Input Sample Time
Conversion Time
Throughput Rate
CS/SHDN Falling Edge to DCLOCK Low
CS/SHDN Falling Edge to DCLOCK Rising Edge
DCLOCK Falling Edge to Current DOUT Not Valid
1.5 2.0 Clk Cycles
12 Clk Cycles
200 kHz
0 ns
30 ns
15 ns
5 FN7877.2
April 19, 2012
5 Page 
ISL267817
Typical Performance Characteristics TA = +25°C, VCC = 5V, VREF = 2.5V, fSAMPLE = 200kHz,
fCLK = 16 * fSAMPLE, unless otherwise specified. (Continued)
30
25
20
15
10
5
0
-50 -25 0
25 50 75 100
TEMPERATURE (°C)
FIGURE 24. REFERENCE CURRENT vs TEMPERATURE (CODE = FF8h)
Functional Description
The ISL267817 is based on a successive approximation register
(SAR) architecture utilizing capacitive charge redistribution
digital to analog converters (DACs). Figure 25 shows a simplified
representation of the converter. During the acquisition phase
(ACQ), the differential input is stored on the sampling capacitors
(CS). The comparator is in a balanced state since the switch
across its inputs is closed. The signal is fully acquired after tACQ
has elapsed, and the switches then transition to the conversion
phase (CONV) so the stored voltage may be converted to digital
format. The comparator will become unbalanced when the
differential switch opens and the input switches transition
(assuming that the stored voltage is not exactly at mid-scale).
The comparator output reflects whether the stored voltage is
above or below mid-scale, which sets the value of the MSB. The
SAR logic then forces the capacitive DACs to adjust up or down by
one quarter of full-scale by switching in binarily weighted
capacitors. Again, the comparator output reflects whether the
stored voltage is above or below the new value, setting the value
of the next lowest bit. This process repeats until all 12 bits have
been resolved.
CONV
+IN
ACQ
ACQ
–IN
ACQ CONV
CONV
VREF
SAR
LOGIC
FIGURE 25. SAR ADC ARCHITECTURAL BLOCK DIAGRAM
An external clock must be applied to the DCLOCK pin to generate
a conversion result. The allowable frequency range for DCLOCK is
10kHz to 3.2MHz (625SPS to 200kSPS). Serial output data is
transmitted on the falling edge of DCLOCK. The receiving device
(FPGA, DSP or Microcontroller) may latch the data on the rising
edge of DCLOCK to maximize set-up and hold times.
A stable, low-noise reference voltage must be applied to the VREF
pin to set the full-scale input range and common-mode voltage. See
“Voltage Reference Input” on page 12 for more details.
ADC Transfer Function
The output coding for the ISL267817 is twos complement. The
first code transition occurs at successive LSB values (i.e., 1 LSB,
2 LSB, and so on). The LSB size is 2*VREF/4096. The ideal
transfer characteristic of the ISL267817 is shown in Figure 26.
011...111
011...110
1LSB = 2•VREF/4096
000...001
000...000
111...111
100...010
100...001
100...000
–VREF
+ ½LSB
0V
+VREF
– 1½LSB
ANALOG INPUT
+IN – (–IN)
+VREF
– 1LSB
FIGURE 26. IDEAL TRANSFER CHARACTERISTICS
Analog Input
The ISL267817 features a fully differential input with a nominal
full-scale range equal to twice the applied VREF voltage. Each
input swings VREF VP-P, 180° out-of-phase from one another for
a total differential input of 2*VREF (refer to Figure 27).
VREF PP
+IN
ISL267817
VCM
VREF PP
–IN
FIGURE 27. DIFFERENTIAL INPUT SIGNALING
11 FN7877.2
April 19, 2012
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ISL267817.PDF ] | |
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