|
|
PDF ISL267452 Data sheet ( Hoja de datos )
| Número de pieza | ISL267452 | |
| Descripción | 555kSPS SAR ADC | |
| Fabricantes | Intersil | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de ISL267452 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
12-Bit, 555kSPS SAR ADC
ISL267452
The ISL267452 is a 12-bit, 555kSPS sampling SAR-type ADC
featuring excellent linearity over supply and temperature
variations, and is drop-in compatible with the AD7452. The
robust, fully-differential input offers high impedance to minimize
errors due to leakage currents, and the specified measurement
accuracy is maintained with input signals up to the supply rails.
The reference accepts inputs from 0.1V to 2.2V for 3V operation
and 0.1V to 3.5V for 5V operation, which provides design
flexibility in a wide variety of applications. The ISL267452 also
features up to 8kV Human Body Model ESD survivability.
The serial digital interface is SPI compatible and is easily
interfaced to all popular FPGAs and microcontrollers. Power
dissipation is 7mW at a sampling rate of 555kSPS, and just 5µW
between conversions utilizing Auto Power-Down mode (with a 5V
supply), making the ISL267452 an excellent solution for remote
industrial sensors and battery-powered instruments.
The ISL267452 is available in an 8 LD SOT-23 package, and is
specified for operation over the Industrial temperature range
(-40°C to +85°C).
Features
• Drop-in Compatible with AD7452
• Differential Input (Span = 2VREF)
• Simple SPI-compatible Serial Digital Interface
• Guaranteed No Missing Codes
• 555kHz Sampling Rate
• 3V or 5V Operation
• Low Operating Current
- 1.25mA at 555kSPS with 3V Supplies
- 1.70mA at 555kSPS with 5V Supplies
• Power-down Current between Conversions: 1µA
• Excellent Differential Non-Linearity
• Low THD: -83dB (typ)
• Pb-Free (RoHS Compliant)
• Available in SOT-23 Package
Applications
• Remote Data Acquisition
• Battery Operated Systems
• Industrial Process Control
• Energy Measurement
• Data Acquisition Systems
• Pressure Sensors
• Flow Controllers
VREF
VDD
VIN+
VIN–
SAR
LOGIC
SERIAL
INTERFACE
SCLK
SDATA
CS
VREF
GND
FIGURE 1. BLOCK DIAGRAM
1.0
0.8
0.6
0.4
0.2
0.0
-0.2
-0.4
-0.6
-0.8
-1.0
0
1024
2048
CODE
3072
FIGURE 2. DIFFERENTIAL LINEARITY ERROR vs CODE
4096
July 26, 2012
FN8255.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2012. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL267452
Absolute Maximum Ratings
Any Pin to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3V to +6.0V
Analog Input to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V
Digital I/O to GND. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V
Digital Input Voltage to GND . . . . . . . . . . . . . . . . . . . . . . .-0.3V to VDD+0.3V
Maximum Current In to Any Pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10mA
ESD Rating
Human Body Model (Tested per JESD22-A114F) . . . . . . . . . . . . . . . . 8kV
Machine Model (Tested per JESD22-A115B) . . . . . . . . . . . . . . . . . 400V
Charged Device Model (Tested per JESD22-C101E). . . . . . . . . . . . 1.5kV
Latch Up (Tested per JESD78C; Class 2, Level A) . . . . . . . . . . . . . . . 100mA
Thermal Information
Thermal Resistance (Typical)
θJA (°C/W) θJC (°C/W)
8 Ld SOT-23 Package (Notes 5, 6). . . . . . . .
135
99
Operating Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40°C to +85°C
Storage Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65°C to +150°C
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150°C
Pb-Free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product
reliability and result in failures not covered by warranty.
NOTES:
5. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
6. For θJC, the “case temp” location is taken at the package top center.
Electrical Specifications VDD = +3.0V to +3.6V, fSCLK = 10MHz, fS = 555kSPS, VREF = 2.0V; VDD = +4.75V to +5.25V, fSCLK = 10MHz,
fS = 555kSPS, VREF = 2.5V; VCM = VREF, unless otherwise noted. Typical values are at TA = +25°C. Boldface limits apply over the operating temperature
range, -40°C to +85°C.
ISL267452
SYMBOL
PARAMETER
TEST CONDITIONS
MIN
(Note 7)
MAX
TYP (Note 7) UNITS
DYNAMIC PERFORMANCE
SINAD Signal-to (Noise + Distortion) Ratio
fIN = 100kHz
VDD = +4.75V to +5.25V
70.0 71.4
dB
fIN = 100kHz
VDD = +3.0V to +3.6V
68.5 70.5
dB
THD Total Harmonic
Distortion
fIN = 100kHz
VDD = +4.75V to +5.25V
-84 -76 dB
fIN = 100kHz
VDD = +3.0V to +3.6V
-84 -74 dB
SFDR Spurious Free Dynamic Range
fIN = 100kHz
VDD = +4.75V to +5.25V
-87 -76 dB
fIN = 100kHz
VDD = +3.0V to +3.6V
-85 -74 dB
IMD Intermodulation Distortion
tpd Aperture Delay
2nd and 3rd order, fIN = 90kHz, 110kHz
-95 dB
1 ns
Δtpd Aperture Jitter
15 ps
β3dB Full Power Bandwidth
@ –3dB
15 MHz
DC ACCURACY
N Resolution
12 Bits
INL Integral Nonlinearity
-1 ±0.4 1 LSB
DNL Differential Nonlinearity
Guaranteed no missed codes to 12 bits
-0.95 ±0.3 0.95 LSB
OFFSET Zero-Code Error
Zero Volt Differential Input
-6 ±0.2 6 LSB
GAIN
Positive Gain Error
Negative Gain Error
± VREF input range
-2 ±0.1 2 LSB
-2 ±0.1 2 LSB
ANALOG INPUT (Note 8)
|AIN| Full-Scale Input Span
2 x VREF
VIN+ - VIN–
V
Absolute Input Voltage Range
VIN+, VIN– VIN+
VIN–
VCM = VREF
VCM±VREF/2
VCM±VREF/2
V
V
5 FN8255.0
July 26, 2012
5 Page 
ISL267452
Analog Input
The ISL267452 features a fully differential input with a nominal
full-scale range equal to twice the applied VREF voltage. Each
input swings VREF VP-P, 180° out-of-phase from one another for
a total differential input of 2*VREF (refer to Figure 21).
Differential signaling offers several benefits over a single-ended
input, such as:
• Doubling of the full-scale input range (and therefore the
dynamic range)
• Improved even order harmonic distortion
• Better noise immunity due to common mode rejection
VREFP-P
VIN+
ISL267452
VCM
VREFP-P
VIN–
FIGURE 21. DIFFERENTIAL INPUT SIGNALING
Figure 22 shows the relationship between the reference voltage
and the full-scale input range for two different values of VREF.
V
5.0
4.0
VIN+
3.0 2.0VP-P
2.0
VIN–
VCM
1.0
t
VREF=2V
V
5.0
4.0
2.5VP-P
VIN+
3.0
VIN–
VCM
2.0
1.0
t
VREF=2.5V
FIGURE 22. RELATIONSHIP BETWEEN VREF AND FULL-SCALE RANGE
Note that there is a trade-off between VREF and the allowable
common mode input voltage (VCM). The full-scale input range is
proportional to VREF; therefore the VCM range must be limited
for larger values of VREF in order to keep the absolute maximum
and minimum voltages on the VIN+ and VIN– pins within
specification. Figures 23 and 24 illustrate this relationship for 5V
and 3V operation, respectively. The dashed lines show the
theoretical VCM range based solely on keeping the VIN+ and
VIN– pins within the supply rails. Additional restrictions are
imposed due to the required headroom of the input circuitry,
resulting in practical limits shown by the shaded area.
VCM
5.0
4.25V
4.0
3.0
3.25V
2.0
1.75V
1.0
0.5 1.0 1.5 2.0 2.5 3.0 3.5
VREF
FIGURE 23. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 5V
VCM
2.5
2.5
2.0 2.0V
1.5
1.0 1.0V
0.5
0.25 0.50 0.75 1.00 1.25 1.50 1.75 2.00
VREF
FIGURE 24. RELATIONSHIP BETWEEN VREF AND VCM FOR VDD = 3V
Voltage Reference Input
An external low-noise reference voltage must be applied to the VREF
pin to set the full-scale input range of the converter. The reference
input accepts voltages ranging from 0.1V to 2.2V for 3V operation
and 0.1V to 3.5V for 5V operation. The device is specified with a
reference voltage of 2.5V for 5V operation and 2.0V for 3V
operation.
Figures 26 and 27 illustrate possible voltage reference options for
the ISL267452. Figure 26 uses the precision ISL21090 voltage
reference, which exhibits exceptionally low drift and low noise. The
ISL21090 must use a power supply greater than 4.7V. The VREF
input pin of the ISL267452 uses very low current, so the decoupling
capacitor can be small (0.1µF).
Figure 27 illustrates the ISL21010 voltage reference being used
with the ISL267452. The ISL21010 series voltage references have
higher noise and drift than the ISL26090 devices, but they consume
very low operating current and are excellent for battery-powered
applications.
11 FN8255.0
July 26, 2012
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet ISL267452.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| ISL267450 | 1MSPS SAR ADCs | Intersil |
| ISL267450A | (ISL267440 / ISL267450A) 1MSPS SAR ADCs | Intersil |
| ISL267452 | 555kSPS SAR ADC | Intersil |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |