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PDF ISL54101A Data sheet ( Hoja de datos )
| Número de pieza | ISL54101A | |
| Descripción | TMDS Regenerators | |
| Fabricantes | Intersil | |
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® Key Features ISL54100A, ISL54101A, ISL54102A
Data Sheet
June 17, 2008
FN6725.0
TMDS Regenerators with Multiplexers
The ISL54100A, ISL54101A, ISL54102A are high-
performance TMDS (Transition Minimized Differential
Signaling) timing regenerators and multiplexers. The
receiver contains a programmable equalizer and a clock
data recovery (CDR) function for each of the 3 TMDS pairs
in an HDMI or DVI signal. The TMDS data outputs of the
ISL5410xA are regenerated and perfectly aligned to the
regenerated TMDS clock signal, creating an extremely
clean, low-jitter DVI/HDMI signal that can be easily
decoded by any TMDS receiver.
The ISL5410xA’s design and package footprint supports
many compound configurations. Two ISL54100As can
create a DualLink 4:1 mux, a 4:2 crosspoint, or an 8:1 mux.
Additional ISL54100As can create larger combinations of
these building blocks. The ISL54102A with its 2:1
multiplexing function serves applications with fewer inputs,
while the ISL54101A can be used as a cable extender, to
clean up a noisy/jittery TMDS source, or to provide a very
stable TMDS signal to a marginal DVI or HDMI receiver.
Certified HDMI 1.3a compliant by the HDMI ATC for the
following features: 12 bit Deep Color (1080i/720p
guaranteed, 1080p typical), x.v.Color™, and all HDMI1.3
audio formats and options.
Block Diagrams
Features
• ISL54100A: 4:1 TMDS regenerator and multiplexer
• ISL54101A: 1:1 TMDS regenerator
• ISL54102A: 2:1 TMDS regenerator and multiplexer
• Clock Data Recovery and Retiming function enables use
as TMDS range extender
• Programmable pre-emphasis on output driver
• Channel activity detect based on input TMDS clock activity
• Symmetrical pinout enables high-performance DualLink,
4:2 crosspoint and 8:1 multiplexing options
• Programmable internal 50Ω, 100Ω, or high-Z termination
• External pins for channel select, activity detection
• Stand-alone or I2C software-controlled operation
• Hardware, software, or automatic channel selection
• Pb-free (RoHS compliant)
Applications
• KVM switches
• A/V receivers
• DVI/HDMI extenders
• Televisions/PC monitors/projectors
TMDS IN (A) 4X2
TMDS IN (B) 4X2
TMDS IN (C) 4X2
TMDS IN (D) 4X2
RECOVERY AND
REGENERATION
TMDS TX
4X2 TMDS OUT
ISL54100A
TMDS IN 4X2
TMDS IN (A) 4X2
TMDS IN (B) 4X2
1
RECOVERY AND
REGENERATION
TMDS TX
4X2 TMDS OUT
ISL54101A
RECOVERY AND
REGENERATION
TMDS TX
4X2 TMDS OUT
ISL54102A
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright Intersil Americas Inc. 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL54100A, ISL54101A, ISL54102A
ISL54100A Pin Configuration
ADDR2 1
PD 2
VD 3
RX2-_B 4
RX2+_B 5
VD 6
GND 7
VD 8
RXC-_A 9
RXC+_A 10
VD 11
RXC-_B 12
RXC+_B 13
VD 14
GND 15
VD 16
GND 17
GND 18
VD 19
RES_TERM 20
VD 21
RES_BIAS 22
GND 23
GND 24
VD 25
RXC-_C 26
RXC+_C 27
VD 28
RXC-_D 29
RXC+_D 30
VD 31
GND 32
VD 33
RX0-_C 34
RX0+_C 35
VD 36
RESET 37
ADDR3 38
102 CH_D_ACTIVE
101 CH_C_ACTIVE
100 CH_B_ACTIVE
99 CH_A_ACTIVE
98 VD
97 GND
96 GND
95 VD_ESD
94 VD
93 GND
92 VD
91 GND
90 TXC+
89 TXC-
88 GND
87 TX2+
86 TX2-
85 GND
84 TX1+
83 TX1-
82 GND
81 TX0+
80 TX0-
79 GND
78 GND
77 VD
76 GND
75 GND
74 VD_ESD
73 VD
72 GND
71 TEST
70 SCL
69 SDA
68 CH_SEL_1
67 CH_SEL_0
66 AUTO_CH_SEL
65 ADDR6
5 FN6725.0
June 17, 2008
5 Page 
ISL54100A, ISL54101A, ISL54102A
Register Listing (Continued)
ADDRESS REGISTER (DEFAULT VALUE)
0x04
Termination Control (0x00)
0x05
Output Options (0x00)
0x06
Data Output Drive (0x00)
BIT(S) FUNCTION NAME
DESCRIPTION
0 Data Termination A 0: Channel A TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel A TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
1 Data Termination B 0: Channel B TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel B TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
2 Data Termination C 0: Channel C TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel C TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
3 Data Termination D 0: Channel D TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel D TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
4 Clk Termination A 0: Channel A TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel A TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
5 Clk Termination B 0: Channel B TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel B TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
6 Clk Termination C 0: Channel C TMDS Clock inputs terminated into 50Ω
(normal operation)
1: Channel C TMDS Clock inputs terminated into 100Ω (for
paralleled inputs)
7 Clk Termination D 0: Channel D TMDS Data inputs terminated into 50Ω
(normal operation)
1: Channel D TMDS Data inputs terminated into 100Ω (for
paralleled inputs)
0 Tri-state Clock
Outputs
0: Normal Operation
1: Clock outputs tri-stated (allows another chip to drive the
output clock pins)
1 Tri-state Data
Outputs
0: Normal Operation
1: Data outputs tri-stated (allows another chip to drive the
output data pins)
2 Invert Output
Polarity
0: Normal Operation
1: The polarity of the TMDS data outputs is inverted
(+ becomes -, - becomes +). TMDS clock unchanged.
3 Reverse Output
Order
0: Normal Operation
1: CH0 data is output on CH2 and CH2 data is output on
CH0. No change to CH1.
3:0 Transmit Current
Transmit Drive Current for data signals, adjustable in
0.125mA steps. Clock current is fixed at 10mA.
0x0: 10mA
0x8: 11mA
0xF: 11.875mA
7:4 Transmit
Pre-emphasis
Drive boost (in 0.125mA steps) added during first half of
each bit period for data signals. Clock signals do not have
pre-emphasis.
0x0: 0mA
0x8: 1mA
0xF: 1.875mA
11 FN6725.0
June 17, 2008
11 Page | ||
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| PDF Descargar | [ Datasheet ISL54101A.PDF ] | |
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