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PDF ISL76321 Data sheet ( Hoja de datos )
| Número de pieza | ISL76321 | |
| Descripción | 16-Bit Long-Reach Video Automotive Grade SERDES | |
| Fabricantes | Intersil | |
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DATASHEET
16-Bit Long-Reach Video Automotive Grade SERDES
with Bi-directional Side-Channel
ISL76321
The ISL76321 is a serializer/deserializer of LVCMOS parallel
video data. The video data presented to the serializer on the
parallel LVCMOS bus is serialized into a high-speed differential
signal. This differential signal is converted back to parallel video
at the remote end by the deserializer. It also transports auxiliary
data bi-directionally over the same link during the video vertical
retrace interval. I2C bus mastering allows the placement of
external slave devices on the remote side of the link. An I2C
controller can be placed on either side of the link allowing
bidirectional I2C communication through the link to the external
devices on the other side. Both chips can be fully configured from
a single controller or independently by local controllers.
Related Literature
• ISL34341 Data Sheet “WSVGA 24-Bit Long-Reach Video
SERDES with Bi-directional Side-Channel”
Features
• 16-bit RGB transport over a single differential pair
• 6MHz to 50MHz pixel clock rates
• AEC-Q100 qualified component
• Bi-directional auxiliary data transport without extra bandwidth
and over the same differential pair
• Hot-plugging with automatic resynchronization every HSYNC
• I2C bus mastering to the remote side of the link with a
controller on either the serializer or deserializer
• Selectable clock edge for parallel data output
• DC-balanced with industry standard 8b/10b line code allows
AC-coupling, providing immunity against ground shifts
• 16 programmable settings each for transmitter amplitude
boost and pre-emphasis and receiver equalization, allow for
longer cable lengths and higher data rates
• Slew rate control and spread spectrum capability on outputs
reduce the potential for EMI
• Same device for serializer and deserializer simplifies inventory
Applications
• Video entertainment systems
• Remote cameras
3.3V
1.8V VDD_IO
16
VIDEO
SOURCE
RGB
VSYNC
HSYNC
DE
PCLK_IN
ISL76321
SERIALIZER
27nF
SERIOP
27nF
SERION
3.3V
1.8V VDD_IO
27nF
SERIOP
27nF
ISL76321
SERION DESERIALIZER
RGB
VSYNC
HSYNC
DE
REF_CLK
PCLK_IN
PCLK_OUT
16
VIDEO
TARGET
VDD_IO
FIGURE 1. TYPICAL APPLICATION
May 1, 2015
FN7803.2
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2011, 2013, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL76321
Ordering Information
PART NUMBER
(Notes 3, 4, 5)
PART
MARKING
TEMP. RANGE
(°C)
PACKAGE
(RoHS Compliant)
PKG.
DWG. #
ISL76321ARZ
ISL76321 ARZ
-40 to +105
48 Ld QFN
L48.7x7C
NOTES:
3. Add “-T*” suffix for tape and reel. Please refer to TB347 for details on reel specifications.
4. These Intersil Pb-free plastic packaged products employ special Pb-free material sets, molding compounds/die attach materials, and 100% matte
tin plate plus anneal (e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations). Intersil Pb-
free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
5. For Moisture Sensitivity Level (MSL), please see device information page for ISL76321. For more information on MSL please see techbrief TB363.
Submit Document Feedback
5
FN7803.2
May 1, 2015
5 Page 
ISL76321
may require the deserializer to be manually reset. A 10ms delay
after the 1.8V supply is powered up guarantees normal
operation.
Power Supply Bypassing and Layout
The serializer and deserializer functions rely on the stable
functioning of PLLs locked to local reference sources or locked to
an incoming signal. It is important that the various supplies
(VDD_P, VDD_AN, VDD_CDR, VDD_TX) be well bypassed over a
wide range of frequencies, from below the typical loop bandwidth
of the PLL to approaching the signal bit rate of the serial data. A
combination of different values of capacitors from 1000pF to
5µF or more with low ESR characteristics is generally required.
The parallel LVCMOS VDD_IO supply is inherently less sensitive,
but since the RGB and SYNC/DATAEN signals can all swing on the
same clock edge, the current in these pins, and the
corresponding GND pins, can undergo substantial current flow
changes. Once again, a combination of different values of
capacitors over a wide range, with low ESR characteristics, is
desirable.
A set of arrangements of this type is shown in Figure 5, where
each supply is bypassed with a ferrite-bead-based choke, and a
range of capacitors. A “choke” is preferable to an “inductor” in
this application, since a high-Q inductor will be likely to cause one
or more resonances with the shunt capacitors, potentially
causing problems at or near those frequencies, while a “lossy”
choke will reflect a high impedance over a wide frequency range.
The higher value capacitor, in particular, needs to be chosen
carefully, with special care regarding its ESR. Very good results
can be obtained with multilayer ceramic capacitors (available
from many suppliers) and generally in small outlines (such as the
1210 outline suggested in the schematic shown in Figure 5),
which provide good bypass capabilities down to a few mΩ at
1MHz to 2MHz. Other capacitor technologies may also be
suitable (perhaps niobium oxide), but “classic” electrolytic
capacitors frequently have ESR values of above 1Ω, that nullify
any decoupling effect above the 1kHz to 10kHz frequency range.
Capacitors of 0.1µF offer low impedance in the 10MHz to 20MHz
region, and 1000pF capacitors in the 100MHz to 200MHz region.
In general, one of the lower value capacitors should be used at
each supply pin on the IC. Figure 5 shows the grounding of the
various capacitors to the pin corresponding to the supply pin.
Although all the ground supplies are tied together, the PCB layout
should be arranged to emulate this arrangement (at least for the
smaller value (high frequency) capacitors), as much as possible.
120Ω
120Ω
120Ω
10µF
0.1µF
10µF
0.1µF
10µF
0.1µF
120Ω
10µF
0.1µF
120Ω
120Ω
10µF
0.1µF
10µF
0.1µF
FIGURE 5. POWER SUPPLY BYPASSING
I2C Interface
The I2C interface allows access to internal registers used to
configure the SERDES and to obtain status information. A
serializer must be assigned a different address than its
deserializer counterpart if the side channel is used. The upper 5
bits are permanently set to 011 11 and the lower 2 bits
determined by pins as follows:
0 1 1 1 1 I2CA1 I2CA0 R/W
Thus, 4 SERDES can reside on the same bus. By convention,
when all address pins are tied low, the device address is referred
to as 0x78.
SCL and SDA are open drain to allow multiple devices to share
the bus. If not used, SCL and SDA should be tied to VDD_IO.
Side Channel Interface
The Side Channel is a mechanism for transferring data between
the two chips on each end of the link. This data is transferred
during video blanking so none of the video bandwidth is used. It
has three basic uses:
• Remote SERDES configuration
• Data exchanges between two processors
• Master Mode I2C commands to remote slaves
This interface allows the user to initialize registers, control and
monitor both SERDES chips from a single microcontroller which
can reside on either side of the serial link. This feature is used to
automatically transport the remote side SERDES chip’s status
back to a local register. The Side Channel needs to be enabled
(the default) for this to work. In the case where there is a
microcontroller on each side of the of the link, data can be
buffered and exchanged between the two. Up to 224 bytes can
be sent in each direction during each VSYNC active period.
Submit Document Feedback 11
FN7803.2
May 1, 2015
11 Page | ||
| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet ISL76321.PDF ] | |
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