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ISL6329 の電気的特性と機能

ISL6329のメーカーはIntersilです、この部品の機能は「Dual PWM Controller Powering AMD SVI Split-Plane Processors」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL6329
部品説明 Dual PWM Controller Powering AMD SVI Split-Plane Processors
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL6329 Datasheet, ISL6329 PDF,ピン配置, 機能
Dual PWM Controller Powering AMD SVI Split-Plane
Processors
ISL6329
The ISL6329 dual PWM controller delivers high efficiency and
tight regulation from two synchronous buck DC/DC converters.
The ISL6329 supports power control of AMD processors, which
operate from a serial VID interface (SVI). The dual output
ISL6329 features a multiphase controller to support the Core
voltage (VDD) and a single phase controller to power the
Northbridge (VDDNB).
A precision core voltage regulation system is provided by a
one-to-six-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in layout
and reduces the number of external components in the
multi-phase section. A single phase PWM controller with
integrated driver provides a second precision voltage regulation
system for the Northbridge portion of the processor. This
monolithic, dual controller with integrated driver solution
provides a cost and space saving power management solution.
For applications that benefit from load line programming to reduce
bulk output capacitors, the ISL6329 features temperature
compensated output voltage droop. The multiphase portion also
includes advanced control loop features for optimal transient
response to load application and removal. One of these features
is highly accurate, fully differential, continuous DCR current
sensing for load line programming and channel current balance.
Dual edge modulation is another unique feature, allowing for
quicker initial response to high di/dt load transients.
The ISL6329 supports Power Savings Mode by dropping the
number of phases to one or two when the PSI_L bit is set. For
even greater power efficiency, diode emulation and gate voltage
optimization are implemented in PSI mode.
Features
• Processor Core Voltage Via Integrated Multiphase Power
Conversion
• Configuration Flexibility
- 1 or 2-Phase Operation with Internal Drivers
- 3,4,5 or 6-Phase Operation with External PWM Drivers
• PSI_L Support
- Phase Shedding for Improved Efficiency at Light Load
- Diode Emulation in PSI mode
- Gate Voltage Optimization
• I2C Interface with 8 Selectable Addresses
• Precision Core Voltage Regulation
- Differential Remote Voltage Sensing
- ±0.6% System Accuracy Over-Temperature
• Optimal Processor Core Voltage Transient Response
- Adaptive Phase Alignment (APA)
- Active Pulse Positioning Modulation
• Fully Differential, Continuous DCR Current Sensing
- Accurate Load Line Programming
- Precision Channel Current Balancing
- Temperature Compensated
• Serial VID Interface Handles up to 3.4MHz Clock Rates
• Two Level Overcurrent Protection Allows for High Current
Throttling (IDD_SPIKE)
• Multi-tiered Overvoltage Protection
• Selectable Switching Frequency up to 1MHz
• Simultaneous Digital Soft-Start of Both Outputs
• Pb-Free (RoHS Compliant)
April 19, 2011
FN7800.0
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 |Copyright Intersil Americas Inc. 2011. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL6329 pdf, ピン配列
ISL6329
Controller Block Diagram
FB_NB
COMP_NB
VSEN_NB
ISEN_NB+
ISEN_NB-
I2C_ADDR
SCL
SDA
VDDPWRGD
OFS
COMP
FB_PSI
FB
RGND
PWROK
VDDIO
SVC
SVD
VSEN
APA
OCP
TCOMP1
TCOMP2
ISEN1+
ISEN1-
ISEN2+
ISEN2-
ISEN3+
ISEN3-
ISEN4+
ISEN4-
ISEN5+
ISEN5-
ISEN6+
ISEN6-
CURRENT
SENSE
I2C
DAC_OFS
NB_OVP
CORE_OVP
VDDPWRGD_TRIP
GVOT_LDO
NUM_PHASES_PSI
NUM_CYCLES_PSI
OFFSET
RGND
NB_REF
UV
LOGIC
OV
LOGIC
NB
FAULT
LOGIC
CH3_OFF
PSI
+
RGND
+
SVI
SLAVE
BUS
E/A
NB_REF
APA
OV
LOGIC
UV
LOGIC
OC
DUAL
OCP
I_TRIP
8
N
SOFT-START
AND
FAULT LOGIC
LOAD APPLY
TRANSIENT
ENHANCEMENT
CLOCK AND
TRIANGLE WAVE
GENERATOR
E/A
RAMP
MOSFET
DRIVER
EN_12V
ENABLE
LOGIC
LDO
POWER-ON
RESET
DROOP
CONTROL
MOSFET
DRIVER
PWM1
PWM2
PWM3
MOSFET
DRIVER
TEMPERATURE
COMPENSATION
CH1 CURRENT
SENSE
CH2 CURRENT
SENSE
CH3 CURRENT
SENSE
CH4 CURRENT
SENSE
CH5 CURRENT
SENSE
CH6 CURRENT
SENSE
ISEN2-
ISEN3-
ISEN4-
ISEN5-
ISEN6-
I_TC_IN
PWM4
PWM5
I_AVG
CHANNEL
CURRENT
BALANCE
PWM6
1
N
I_TC_IN
1
8
EN_12V
PH3/PH4/PH5/PH6
POR
CHANNEL
DETECT
ISEN2-
ISEN3-
ISEN4-
ISEN5-
ISEN6-
PWM3
SIGNAL
LOGIC
PWM4
SIGNAL
LOGIC
PWM5
SIGNAL
LOGIC
PWM6
SIGNAL
LOGIC
GND
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
PVCC
EN
VCC
GVOT
BOOT1
UGATE1
PHASE1
LGATE1
DRPCTRL
FS
BOOT2
UGATE2
PHASE2
LGATE2
PWM3
PWM4
PWM5
PWM6
3 FN7800.0
April 19, 2011


3Pages


ISL6329 電子部品, 半導体
ISL6329
Functional Pin Descriptions (Continued)
PIN NAME
SDA
VCC
RSVD
OFS
OCP
TCOMP1, TCOMP2
RGND
VSEN
FB_PSI
FB
COMP
FS
APA
ISENn+, ISENn-,
ISEN_NB+, ISEN_NB-
PHASE1, PHASE2
GND
EN
UGATE1, UGATE2
PIN NUMBER
9
DESCRIPTION
Connect this pin to the bidirectional data line of the I2C bus, which is a logic level input/output signal.
All I2C data is sent over this line, including the address of the device the bus is trying to communicate
with and what functions the device should perform.
10 VCC is the bias supply for the ICs small-signal circuitry. Connect this pin to a +5V supply and decouple
using a quality 0.1µF ceramic capacitor.
11 RESERVED. Connect this pin directly to the VCC pin.
12 The OFS pin provides a means to program a DC current for generating an offset voltage across the resistor
between FB and VSEN. The offset current is generated via an external resistor and precision internal
voltage references. The polarity of the offset is selected by connecting the resistor to GND or VCC. For no
offset, the OFS pin should be left unconnected.
13 A capacitor from this pin to ground determines the time that the regulator is allowed to service a load
current spike that exceeds the internal OCP trip point.
14, 15
These two pins are used to compensate the inductor current sensing for fluctuations due to
temperature.
16 Inverting input to the Core and Northbridge regulator precision differential remote-sense amplifiers. This
pin should be connected to the remote ground sense pin of the processor core, VSS_SENSE.
17 Non-inverting input to the Core regulator precision differential remote-sense amplifier. This pin should be
connected to the remote Core sense pin of the processor, VDD_SENSE.
18 In PSI mode this pin is internally shorted to the FB pin to augment the feedback compensation network
for the lower phase count.
19 Inverting input to the internal error amplifier for the Core regulator.
20 Output of the internal error amplifier for the Core regulator.
21 This is a dual function pin. A resistor, placed from FS to either Ground or VCC sets the switching
frequency of both controllers. Refer to Equation 1 for proper resistor calculation.
RT
=
[ 10.61
10
1.035
log
(
fs)
]
(EQ. 1)
If the resistor is tied to ground, the number of active phases in PSI mode is 1. If the resistor is tied to
VCC, the number of active phases in PSI mode is 2.
22 Allows for programming of the Auto Phase Alignment threshold. A resistor in parallel with a capacitor
to ground is used to set this threshold.
23, 24, 25, 26,
27, 28, 53, 54,
55, 56, 57, 58,
59, 60
40, 29
These pins are used for differentially sensing the corresponding channel output currents. The sensed
currents are used for channel balancing, protection, and core load line regulation.
Connect ISEN- to the node between the RC sense elements surrounding the inductor of the respective
channel. Tie the ISEN+ pin to the other end of the sense capacitor through a resistor, RISEN. The voltage
across the sense capacitor is proportional to the inductor current. The sense current, therefore, is
proportional to the inductor current and scaled by the DCR of the inductor and RISEN.
Connect these pins to the sources of the corresponding upper MOSFETs. These pins are the return path
for the upper MOSFET drives.
30, 32, 61
Bias and reference ground for the IC. The GND connection for the ISL6329 is made with three pins and
through the thermal pad on the bottom of the package.
31 This pin is a threshold-sensitive (approximately 0.85V) system enable input for the controller. Held low, this
pin disables both CORE and NB controller operation. Pulled high, the pin enables both controllers for
operation.
A second function of this pin is to provide driver bias monitor for external drivers. A resistor divider with the
center tap connected to this pin from the drive bias supply prevents enabling the controller before
insufficient bias is provided to external driver. The resistors should be selected such that when the POR-
trip point of the external driver is reached, the voltage at this pin meets the above mentioned threshold
level.
39, 33
Connect this pin to the corresponding upper MOSFET gate. This pin provides the PWM-controlled gate
drive for the upper MOSFET and is monitored for shoot-through prevention purposes.
6 FN7800.0
April 19, 2011

6 Page



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