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PDF ISL6328A Data sheet ( Hoja de datos )
| Número de pieza | ISL6328A | |
| Descripción | Dual PWM Controller | |
| Fabricantes | Intersil | |
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DATASHEET
Dual PWM Controller For Powering AMD SVI Split-Plane
Processors
ISL6328A
The ISL6328A dual PWM controller delivers high efficiency
and tight regulation from two synchronous buck DC/DC
converters. The ISL6328A supports power control of AMD
processors, which operate from a serial VID interface (SVI). The
dual output ISL6328A features a multiphase controller to
support the Core voltage (VDD) and a single phase controller to
power the Northbridge (VDDNB).
A precision core voltage regulation system is provided by a
one-to-four-phase PWM voltage regulator (VR) controller. The
integration of two power MOSFET drivers adds flexibility in
layout and reduces the number of external components in the
multiphase section. A single phase PWM controller with
integrated driver provides a second precision voltage
regulation system for the Northbridge portion of the processor.
This monolithic, dual controller with an integrated driver
solution provides a cost and space saving power management
solution.
For applications that benefit from load line programming to
reduce bulk output capacitors, the ISL6328A features
temperature compensated output voltage droop. The multiphase
portion also includes advanced control loop features for
optimal transient response to load application and removal.
One of these features is highly accurate, fully differential,
continuous DCR current sensing for load line programming
and channel current balance. Dual edge modulation is another
unique feature, allowing for quicker initial response to high
di/dt load transients.
The ISL6328A supports Power Savings Mode by dropping the
number of phases when the PSI_L bit is set.
Features
• Processor core voltage via integrated multiphase power
conversion
• Configuration flexibility
- 1 or 2-phase operation with internal drivers
- 3 or 4-phase operation with external PWM drivers
• PSI_L support
- Phase shedding for improved efficiency at light load
- Diode emulation in PSI mode
- Gate voltage optimization
• Precision core voltage regulation
- Differential remote voltage sensing
- ±0.6% system accuracy over-temperature
• Optimal processor core voltage transient response
- Adaptive phase alignment (APA)
- Active pulse positioning modulation
• Fully differential, continuous DCR current sensing
- Accurate load line programming
- Precision channel current balancing
- Temperature compensated
• Serial VID interface handles up to 3.4MHz clock rates
• Two level overcurrent protection allows for high current
throttling (IDD_SPIKE)
• Multitiered overvoltage protection
• Selectable switching frequency up to 1MHz
• Simultaneous digital soft-start of both outputs
February 13, 2015
FN7986.1
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2012, 2015. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Typical Application
VCC
+5V
ISL6328A
CS1-
CS1+
CS2-
CS2+
CS3-
CS3+
CS4-
CS4+
CS_NB-
CS_NB+
+12V
ENABLE
CORE_FB
VCC RSVD
ISEN1-
TCOMP1
ISEN1+
TCOMP2
ISEN2-
ISEN2+
PWM3
PWM4
ISEN3-
ISEN3+
ISL6328A
PVCC
GVOT
ISEN4-
ISEN4+
BOOT1
ISEN_NB-
ISEN_NB+
UGATE1
PHASE1
LGATE1
DRPCTRL
FS
OFS
OCP
SVC
SVD
PWROK
VDDPWRGD
EN
APA
BOOT2
UGATE2
PHASE2
LGATE2
VSEN
RGND
BOOT_NB
UGATE_NB
PHASE_NB
LGATE_NB
FB_PSI
FB
COMP
VSEN_NB
FB_NB
COMP_NB
GND
PWM3
PWM4
+12V
+12V
+12V
CS1-
CS1+
+12V
+12V
CS3-
CS3+
CS2-
CS2+
CS4-
CS4+
ISL6614
BOOT1 PWM1
PWM3
PWM2
PWM4
UGATE1
PHASE1
+12V
LGATE1 PVCC
VCC
BOOT2
GND
UGATE2
PHASE2
PGND
LGATE2
CORE_FB
+12V
CS_NB-
CS_NB+
CORE
CPU
NORTHBRIDGE
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5
FN7986.1
February 13, 2015
5 Page 
ISL6328A
Electrical Specifications Boldface limits apply across the operating temperature range, 0°C to +70°C. (Continued)
PARAMETER
TEST CONDITIONS
MIN MAX
(Note 6) TYP (Note 6) UNITS
POWER GOOD
Overvoltage Threshold
VSEN Rising
VDAC +
220mV
VDAC +
325mV
V
Undervoltage Threshold
VSEN Falling
VDAC -
345mV
VDAC -
190mV
mV
Power-good Hysteresis
50 mV
OVERVOLTAGE PROTECTION
OVP Trip Level
OVP Lower Gate Release Threshold
VDAC = 1.1V
1.75
0.35
1.79
1.85
V
V
SWITCHING TIME (Note 7) [See “Timing Diagram” on page 12]
UGATE Rise Time
LGATE Rise Time
UGATE Fall Time
LGATE Fall Time
UGATE Turn-on Nonoverlap
LGATE Turn-on Nonoverlap
GATE DRIVE RESISTANCE
tRUGATE; VPVCC = 8V, 3nF Load, 10% to 90%
26 ns
tRLGATE; VPVCC = 8V, 3nF Load, 10% to 90%
18 ns
tFUGATE; VPVCC = 12V, 3nF Load, 90% to 10% 18 ns
tFLGATE; VPVCC = 12V, 3nF Load, 90% to 10%
12 ns
tPDHUGATE; VPVCC = 12V, 3nF Load, Adaptive
10 ns
tPDHLGATE; VPVCC = 12V, 3nF Load, Adaptive
10 ns
Upper Drive Source Resistance
Upper Drive Sink Resistance
Lower Drive Source Resistance
Lower Drive Sink Resistance
SVI INTERFACE
VPVCC = 12V, 15mA Source Current
VPVCC = 12V, 15mA Sink Current
VPVCC = 12V, 15mA Source Current
VPVCC = 12V, 15mA Sink Current
2.5 Ω
2.0 Ω
1.6 Ω
1.1 Ω
SVC, SVD Input HIGH (VIH)
FS resistor tied to GND
0.85
V
SVC, SVD Input LOW (VIL)
FS resistor tied to GND
0.45
V
SVC, SVD Input HIGH (VIH)
FS resistor tied to VCC
1.05
V
SVC, SVD Input LOW (VIL)
FS resistor tied to VCC
0.55
V
SVD Low Level Output Voltage
510Ω Resistor to 1.8V
0.4 V
SVC, SVD Leakage (Note 7)
±5 µA
NOTES:
6. Parameters with MIN and/or MAX limits are 100% tested at +25°C, unless otherwise specified. Temperature limits established by characterization
and are not production tested.
7. Limits should be considered typical and are not production tested.
Submit Document Feedback 11
FN7986.1
February 13, 2015
11 Page | ||
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| PDF Descargar | [ Datasheet ISL6328A.PDF ] | |
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