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ISL78268 の電気的特性と機能

ISL78268のメーカーはIntersilです、この部品の機能は「55V Synchronous Buck Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL78268
部品説明 55V Synchronous Buck Controller
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL78268 Datasheet, ISL78268 PDF,ピン配置, 機能
DATASHEET
55V Synchronous Buck Controller with Integrated 3A
Driver
ISL78268
The ISL78268 is a grade 1, automotive, synchronous buck
controller with integrated high/low side MOSFET drivers. It
supports a wide operating input voltage range of 5V to 55V
and up to 60V at VIN when not switching. The integrated driver
offers adaptive dead-time control and is capable of supplying
up to 2A sourcing and 3A sinking current, allowing the
ISL78268 to support power stages designed for a wide range
of loads, from under 1A to over 25A.
ISL78268’s fully synchronous architecture enables power
conversion with very high efficiency and improved thermal
performance over standard buck converters. The ISL78268 also
offers diode emulation mode for improved light load efficiency.
While ISL78268 is a peak current mode PWM controller, it
also includes a dedicated average output current modulation
loop, which achieves constant output current limiting for
applications such as battery charging, super-cap charging, and
temperature control systems where a constant current must
be provided.
The ISL78268 supports switching frequencies from 50kHz to
1.1MHz allowing the user the flexibility to trade-off switching
frequency and efficiency against the size of external
components.
The ISL78268 offers comprehensive protection features. It
includes robust current protection with cycle-by-cycle peak
current limiting, average current limiting, and a selectable
hiccup or latch-off fault responses. In addition, it offers
protection against over-temperature, as well as input and
output overvoltages.
Features
• Wide input range 5V to 55V (switching); withstand 60V
(non-switching)
• Integrated 2A sourcing, 3A sinking MOSFET drivers
• Constant current regulation/limiting - dedicated average
current control loop
• Adjustable switching frequency or external synchronization
from 50kHz up to 1.1MHz
• Low shutdown current, IQ <1µA
• Peak current mode control with adjustable slope
compensation
• Selectable diode emulation mode for high efficiency at light
load
• Input and output OVP, cycle-by-cycle current limiting,
average current OCP, OTP
• Selectable hiccup or latch-off fault responses
• Pb-free 24 Ld 4x4 QFN package (RoHS compliant)
• AEC-Q100 qualified
Applications
• Automotive power
• Telecom and industrial power supplies
• General purpose power
• Supercap charging
Related Literature
AN1946, “ISL78268EVAL1Z Evaluation Board User Guide”
VIN
EN_IC
PVCC
EN
VCC
VIN
ISEN1P
ISEN1N
IMON/DE
PVCC
BOOT
FSYNC
PLL_COMP
ISL78268
UG
PH
LG
SLOPE
COMP
SS
ISEN2P
ISEN2N
FB
HIC/LATCH
SGND PGND
CLKOUT
PGOOD
PVCC
VOUT
VCC
POWER GOOD
FIGURE 1. SIMPLIFIED TYPICAL APPLICATION SCHEMATIC
100
95
90
85
VIN = 24V
VIN = 15V
80
VIN = 36V
75
70 VIN = 55V
65
60
55
VOUT = 12V, TA = +25°C
50
012345
IOUT (A)
FIGURE 2. EFFICIENCY CURVES (ISL78268EVAL1Z/DE MODE)
December 12, 2014
FN8657.3
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2014. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL78268 pdf, ピン配列
Pin Configuration
ISL78268
ISL78268
(24 LD 4x4 QFN)
TOP VIEW
24 23 22 21 20 19
SLOPE 1
18 BOOT
FB 2
17 UG
COMP 3
SS 4
EPAD
16 PH
15 LG
IMON/DE 5
14 PVCC
PGOOD 6
13 PGND
7 8 9 10 11 12
Functional Pin Description
PIN NAME PIN #
DESCRIPTION
SLOPE
1 This pin programs the slope of the internal slope compensation. A resistor should be connected from the SLOPE pin to GND. Please refer
to “Adjustable Slope Compensation” on page 24 for how to choose this resistor value.
FB 2 The inverting input of the transconductance amplifier. A resistor divider must be placed between the FB pin and the output rail to
set the output voltage.
COMP
3 The output of the transconductance amplifier. Place the compensation network between the COMP pin and GND for compensation loop
design.
SS 4 Use this pin to set up the desired soft-start time. A capacitor placed from SS to GND will set up the soft-start ramp rate and in turn
determine the soft-start time.
IMON/DE
IMON/DE is a bifunctional pin as either the average current monitor/protection or switching mode selection (Diode Emulation (DE)
mode or Forced PWM mode).
1. If IMON/DE pin is connected to VCC (higher than VCC - 0.7V), the device operates in Forced PWM mode and the average current
monitoring/limiting feature is disabled.
2. If a resistor (and a filter capacitor in parallel) is connected between IMON/DE and GND, the device operates in DE mode and
5
the average current monitoring/limiting feature is enabled. A current which is proportional to the current sensed at ISEN2 is
sourced from the IMON/DE pin. With an R/C network at the IMON/DE pin to GND, the voltage at IMON/DE pin describes
average output current.
When average current monitoring/limiting feature is enabled and DE mode is selected;
1. If IMON/DE is higher than 2V, the device enters Average Current Protection mode with the hiccup/latch-off as the fault response.
2. If IMON/DE reaches to 1.6V, the device enters the Average Constant Current control loop.
3. If the IMON/DE pin voltage is lower than 1.6V (typ), the device operates as a normal buck regulator in DE mode.
PGOOD
6 Provides an open-drain Power-Good signal. When the output voltage is within +15/-12% of the nominal output regulation point and
soft-start is completed, the internal PGOOD open-drain transistor is open. It will be pulled low once output UV/OV or input OV conditions
are detected. Requires pull-up resistor connecting to VCC.
FSYNC
7 The oscillator switching frequency is adjusted with a resistor from this pin to GND. The internal oscillator locks to the rising edge of
a square pulse waveform if this pin is driven by an external clock. There is a 325ns delay from the FSYNC pin’s input clock rising
edge to UG rising edge.
SGND
8 Signal ground pin; the reference of internal analog circuits. Connect this pin to a large quiet copper ground plane. In PCB layout
planning, avoid having switching current flowing into the SGND area (including the IC PAD that is connected to the quiet large copper
ground plane also).
Submit Document Feedback
3
FN8657.3
December 12, 2014


3Pages


ISL78268 電子部品, 半導体
Block Diagram
VIN
PVCC
VCC
EN
SS
5.2V
LDO
1/30
VIN/30
+
-
VREF_VINOV
POR
PLL
OVER
TEMP
1.2V
3.4V
5µA
INITIALIZATION
DELAY
EN_SS
SOFT-START
LOGIC
Vin_OV
1.15VREF +
FB -
-
0.87VREF +
EN_SW
HICCUP/
LATCHOFF
OC_AVG
Vo_OV
Vo_UV
SS_DONE
VREF = 1.6V
+
+ Gm
FB -
COMP
VCC - 0.7V
1.6V
+ Gm
-
IMON/DE
SGND
SGND
OC_AVG
2V
+
-
OC1
FAULT
SGND
CLOCK
S
R1
R2
OC2
OC1
Q
ISEN1
ISEN1_OC2
+
-
93µA ISEN1_OC1
+
-
70µA
PWM CONTROL
(ISEN2+68µA)/8
ZERO
CROSS
DETECTION
ISEN2_ZCD
NEGATIVE
OC
ISEN2
ISEN2_Neg
-50µA
PGOOD
CLOCK
VCO
ISLOPE
SLOPE
COMPENSATION
CSA1
112µA
AV = 1
112µA
PVCC
PGND
CSA2
112µA
AV = 1
112µA
N.C.
EPAD
HIC/LATCH
FSYNC
PLL_COMP
CLKOUT
SLOPE
ISEN1P
ISEN1N
BOOT
UG
PH
LG
PGND
ISEN2P
ISEN2N

6 Page



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部品番号部品説明メーカ
ISL78268

55V Synchronous Buck Controller

Intersil
Intersil


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