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PDF ISL6754 Data sheet ( Hoja de datos )
| Número de pieza | ISL6754 | |
| Descripción | ZVS Full-Bridge PWM Controller | |
| Fabricantes | Intersil | |
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DATASHEET
ZVS Full-Bridge PWM Controller with Adjustable
Synchronous Rectifier Control
ISL6754
The ISL6754 is a high performance extension of the Intersil
family of Zero-Voltage Switching (ZVS) full-bridge PWM
controllers. Like the ISL6752, it achieves ZVS operation by
driving the upper bridge FETs at a fixed 50% duty cycle while
the lower bridge FETs are trailing-edge modulated with
adjustable resonant switching delays.
Adding to the ISL6752’s feature set are average current
monitoring and soft-start. The average current signal may be
used for average current limiting, current sharing circuits and
average current mode control. Additionally, the ISL6754
supports both voltage- and current-mode control.
The ISL6754 features complemented PWM outputs for
Synchronous Rectifier (SR) control. The complemented
outputs may be dynamically advanced or delayed relative to
the PWM outputs using an external control voltage.
This advanced BiCMOS design features precision dead time
and resonant delay control, and an oscillator adjustable to
2MHz operating frequency. Additionally, multi-pulse
suppression ensures alternating output pulses at low duty
cycles where pulse skipping may occur.
Applications
• ZVS full-bridge converters
• Telecom and datacom power
• Wireless base station power
• File server power
• Industrial power systems
Features
• Adjustable resonant delay for ZVS operation
• Synchronous rectifier control outputs with adjustable
delay/advance
• Voltage- or current-mode control
• 3% current limit threshold
• Adjustable average current limit
• Adjustable dead time control
• 175µA start-up current
• Supply UVLO
• Adjustable oscillator frequency up to 2MHz
• Internal over-temperature protection
• Buffered oscillator sawtooth output
• Fast current sense to output delay
• Adjustable cycle-by-cycle peak current limit
• 70ns leading edge blanking
• Multi-pulse suppression
• Pb-free (RoHS compliant)
Related Literature
• AN1603, “ISL6752/54EVAL1Z ZVS DC/DC Power Supply
with Synchronous Rectifiers User Guide”
• AN1619, “Designing with ISL6752DBEVAL1Z and
ISL6754DBEVAL1Z Control Cards”
Pin Configuration
ISL6754
(20 LD QSOP)
TOP VIEW
VREF 1
VERR 2
CTBUF 3
RTD 4
RESDEL 5
CT 6
FB 7
RAMP 8
CS 9
IOUT 10
20 SS
19 VADJ
18 VDD
17 OUTLL
16 OUTLR
15 OUTUL
14 OUTUR
13 OUTLLN
12 OUTLRN
11 GND
June 2, 2016
FN6754.2
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Copyright Intersil Americas LLC 2008, 2016. All Rights Reserved
Intersil (and design) is a trademark owned by Intersil Corporation or one of its subsidiaries.
All other trademarks mentioned are the property of their respective owners.
1 page  
Typical Application - High Voltage Input Primary Side Control ZVS Full-Bridge Converter
VI N+
CR2
T3 CR3
+
C1
400 VDC
Q8A
Q8B
Q1
R15
C2
VI N-
Q6A
Q4 Q6B
CR1
T2
R6
R5
R1
R4
Q10A
Q10B
C4
R16
C3
Q5A
Q5B
Q2
Q9A
Q9B
Q7A
Q7B
Q3
T1
R17
C13
Q12
Q13
R13
R7
1 VREF
SS 20
2 VERR
VADJ 19
3 CTBUF
VDD 18
R8
4 RTD
OUTLL 17
5 RESDEL OUTLR 16
6 CT
OUTUL 15
7 FB
OUTUR 14
8 RAMP OUTLLN 13
9 CS
U1
10 IOUT
OUTLRN 12
GND 11
R11 U1
EL7212
U5
C12 T4
CR4
EL7212
R21
U4
R22
R18
L1
C15
C16
+
C14
+ VOUT
RETURN
R20
R19
R23
C17
C18
R24
BIAS
VDD
R12
C9
R2 R3
C5 C6 C7 C8
R9
R10
C10
R14
C11
U2
U3
TL431
R25
FIGURE 2. HIGH VOLTAGE INPUT PRIMARY SIDE CONTROL ZVS FULL-BRIDGE CONVERTER
5 Page 
ISL6754
Functional Description
Features
The ISL6754 PWM is an excellent choice for low cost ZVS full-
bridge applications requiring adjustable synchronous rectifier
drive. With its many protection and control features, a highly
flexible design with minimal external components is possible.
Among its many features are a very accurate overcurrent limit
threshold, thermal protection, a buffered sawtooth oscillator
output suitable for slope compensation, synchronous rectifier
outputs with variable delay/advance timing, and adjustable
frequency.
If synchronous rectification is not required, please consider the
ISL6755 controller.
Oscillator
The ISL6754 has an oscillator with a programmable frequency
range to 2MHz, which can be programmed with a resistor and
capacitor.
The switching period is the sum of the timing capacitor charge
and discharge durations. The charge duration is determined by
CT and a fixed 200µA internal current source. The discharge
duration is determined by RTD and CT.
tC 11.5 103 CT
S
(EQ. 1)
tD 0.06 RTD CT + 50 10–9
S
(EQ. 2)
tSW = tC + tD = f--S--1--W----
S
(EQ. 3)
Where tC and tD are the charge and discharge times,
respectively, CT is the timing capacitor in Farads, RTD is the
discharge programming resistance in ohms, tSW is the oscillator
period, and fSW is the oscillator frequency. One output switching
cycle requires two oscillator cycles. The actual times will be
slightly longer than calculated due to internal propagation delays
of approximately 10ns/transition. This delay adds directly to the
switching duration, but also causes overshoot of the timing
capacitor peak and valley voltage thresholds, effectively
increasing the peak-to-peak voltage on the timing capacitor.
Additionally, if very small discharge currents are used, there will
be increased error due to the input impedance at the CT pin. The
maximum recommended current through RTD is 1mA, which
produces a CT discharge current of 20mA.
The maximum duty cycle, D, and percent Dead Time, DT, can be
calculated from:
D = t--S-t--C-W----
(EQ. 4)
DT = 1 – D
(EQ. 5)
Overcurrent Operation
Two overcurrent protection mechanisms are available to the
power supply designer. The first method is cycle-by-cycle peak
overcurrent protection which provides fast response. The
cycle-by-cycle peak current limit results in pulse-by-pulse duty cycle
reduction when the current feedback signal exceeds 1.0V. When
the peak current exceeds the threshold, the active output pulse is
immediately terminated. This results in a decrease in output
voltage as the load current increases beyond the current limit
threshold. The ISL6754 operates continuously in an overcurrent
condition without shutdown.
The second method is a slower, averaging method which
produces constant or “brick-wall” current limit behavior. If
voltage-mode control is used, the average overcurrent protection
also maintains flux balance in the transformer by maintaining
duty cycle symmetry between half-cycles. If voltage-mode control
is used in a bridge topology, it should be noted that peak current
limit results in inherently unstable operation. The DC blocking
capacitors used in voltage-mode bridge topologies become
unbalanced, as does the flux in the transformer core. Average
current limit will prevent the instability and allow continuous
operation in current limit provided the control loop is designed
with adequate bandwidth.
The propagation delay from CS exceeding the current limit
threshold to the termination of the output pulse is increased by
the Leading Edge Blanking (LEB) interval. The effective delay is
the sum of the two delays and is nominally 105ns.
The current sense signal applied to the CS pin connects to the
peak current comparator and a sample and hold averaging
circuit. After a 70ns Leading Edge Blanking (LEB) delay, the
current sense signal is actively sampled during the on time, the
average current for the cycle is determined, and the result is
amplified by 4x and output on the IOUT pin. If an RC filter is
placed on the CS input, its time constant should not exceed
~50ns or significant error may be introduced on IOUT.
CHANNEL 1 (YELLOW): OUTLL
CHANNEL 3 (BLUE): CS
CHANNEL 2 (RED): OUTLR
CHANNEL 4 (GREEN): IOUT
FIGURE 8. CS INPUT vs IOUT
Figure 8 on page 11 shows the relationship between the CS
signal and IOUT under steady state conditions. IOUT is 4x the
Submit Document Feedback 11
FN6754.2
June 2, 2016
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet ISL6754.PDF ] | |
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