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PDF ISL6744A Data sheet ( Hoja de datos )
| Número de pieza | ISL6744A | |
| Descripción | Intermediate Bus PWM Controller | |
| Fabricantes | Intersil | |
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Data Sheet
October 8, 2007
ISL6744A
FN6554.0
Intermediate Bus PWM Controller
The ISL6744A is a low cost, primary side, double-ended
controller intended for applications using full and half-bridge
topologies for unregulated DC/DC converters. It is a voltage-
mode PWM controller designed for half-bridge and full-
bridge power supplies. It provides precise control of
switching frequency, adjustable soft-start, precise deadtime
control with deadtimes as low as 35ns, and overcurrent
shutdown. The ISL6744A is identical to the ISL6744, but is
optimized for higher noise environments.
Low start-up and operating currents allow for easy biasing in
both AC/DC and DC/DC applications. This advanced
BiCMOS design features low start-up and operating
currents, adjustable switching frequency up to 1MHz, 1A
FET drivers, and very low propagation delays for a fast
response to overcurrent faults.
Ordering Information
PART
NUMBER
PART
TEMP.
PKG.
MARKING RANGE (°C) PACKAGE DWG. #
ISL6744AAUZ 6744A
(Note)
-40 to +105 8 Ld MSOP M8.118
(Pb-free)
ISL6744AABZ 6744AABZ
(Note)
-40 to +105 8 Ld SOIC M8.15
(Pb-free)
*Add “-T” or “-TK” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ special
Pb-free material sets; molding compounds/die attach materials and
100% matte tin plate PLUS ANNEAL - e3 termination finish, which is
RoHS compliant and compatible with both SnPb and Pb-free soldering
operations. Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free requirements of
IPC/JEDEC J STD-020.
Features
• Precision Duty Cycle and Deadtime Control
• 100µA Start-up Current
• Adjustable Delayed Overcurrent Shutdown and Restart
• Adjustable Oscillator Frequency Up to 2MHz
• 1A MOSFET Gate Drivers
• Adjustable Soft-Start
• Internal Over Temperature Protection
• 35ns Control to Output Propagation Delay
• Small Size and Minimal External Component Count
• Input Undervoltage Protection
• Pb-Free (RoHS Compliant)
Applications
• Telecom and Datacom Isolated Power
• DC Transformers
• Bus Converters
Pinout
ISL6744A
(SOIC, MSOP)
TOP VIEW
SS 1
RTD 2
CS 3
CT 4
8 VDD
7 OUTB
6 OUTA
5 GND
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2007. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6744A
Electrical Specifications
Recommended operating conditions unless otherwise noted. Refer to Block Diagram and Typical Application
schematic. 9V < VD < 16V, RTD = 51.1kΩ, CT = 470pF, TA = -40°C to +105°C (Note 3), Typical values are at
TA = +25°C (Continued)
PARAMETER
TEST CONDITIONS
MIN
TYP
MAX
UNITS
OSCILLATOR
Charge Current
143 156 170
μA
RTD Voltage
Discharge Current Gain
1.925 2 2.075 V
45 - 65 μA/μA
CT Valley Voltage
CT Peak Voltage
SOFT-START
Charging Current
0.75
2.70
45
0.8
2.80
-
0.85
2.90
68
V
V
µA
SS Clamp Voltage
3.8 4.0 4.2
V
Overcurrent Shutdown Threshold Voltage
(Note 4)
- 3.9 -
V
Overcurrent Discharge Current
12 15 23 μA
Reset Threshold Voltage
(Note 4)
0.25 0.27 0.30
V
OUTPUT
High Level Output Voltage (VOH)
Low Level Output Voltage (VOL)
Rise Time
Fall Time
THERMAL PROTECTION
VDD - VOUTA or VOUTB,
IOUT = -100mA
IOUT = 100mA
CGATE = 1nF, VDD = 12V
CGATE = 1nF, VDD = 12V
-
0.5 2.0
V
-
0.5 1.0
V
- 17 60 ns
- 20 60 ns
Thermal Shutdown
(Note 4)
- 145 -
°C
Thermal Shutdown Clear
(Note 4)
- 130 -
°C
Hysteresis, Internal Protection
(Note 4)
- 15 - °C
NOTES:
3. Specifications at -40°C and +105°C are guaranteed by +25°C test with margin limits.
4. Limits established by characterization and are not production tested.
5 FN6554.0
October 8, 2007
5 Page 
ISL6744A
∅0.358
∅0.689
0.807
0.639
0.403
FIGURE 7C. INT. LAYER 2: 2 TURNS PRIMARY WINDING
0.169
0.000
0.000 0.184
0.479
0.774 1.054
FIGURE 7G. PWB DIMENSIONS
FIGURE 7D. INT. LAYER 3: 2 TURNS PRIMARY WINDING
FIGURE 7E. INT. LAYER 4: 1 TURN SECONDARY WINDING
FIGURE 7F. BOTTOM LAYER: 1 TURN SECONDARY AND SR
WINDINGS
MOSFET Selection
The criteria for selection of the primary side half-bridge FETs
and the secondary side synchronous rectifier FETs is largely
based on the current and voltage rating of the device.
However, the FET drain-source capacitance and gate
charge cannot be ignored.
The zero voltage switch (ZVS) transition timing is dependent
on the transformer’s leakage inductance and the
capacitance at the node between the upper FET source and
the lower FET drain. The node capacitance is comprised of
the drain-source capacitance of the FETs and the
transformer parasitic capacitance. The leakage inductance
and capacitance form an LC resonant tank circuit which
determines the duration of the transition. The amount of
energy stored in the LC tank circuit determines the transition
voltage amplitude. If the leakage inductance energy is too
low, ZVS operation is not possible and near or partial ZVS
operation occurs. As the leakage energy increases, the
voltage amplitude increases until it is clamped by the FET
body diode to ground or VIN, depending on which FET
conducts. When the leakage energy exceeds the minimum
required for ZVS operation, the voltage is clamped until the
energy is transferred. This behavior increases the time
window for ZVS operation. This behavior is not without
consequences, however. The transition time and the period
of time during which the voltage is clamped reduces the
effective duty cycle.
The gate charge affects the switching speed of the FETs.
Higher gate charge translates into higher drive requirements
and/or slower switching speeds. The energy required to
drive the gates is dissipated as heat.
The maximum input voltage, VIN, plus transient voltage,
determines the voltage rating required. With a maximum
input voltage of 53V for this application, and if we allow a
10% adder for transients, a voltage rating of 60V or higher
will suffice.
11 FN6554.0
October 8, 2007
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