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ISL8700 の電気的特性と機能

ISL8700のメーカーはIntersilです、この部品の機能は「Adjustable Quad Sequencer」です。


製品の詳細 ( Datasheet PDF )

部品番号 ISL8700
部品説明 Adjustable Quad Sequencer
メーカ Intersil
ロゴ Intersil ロゴ 




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ISL8700 Datasheet, ISL8700 PDF,ピン配置, 機能
®
Data Sheet
ISL8700, ISL8701, ISL8702
March 21, 2008
FN9250.2
Adjustable Quad Sequencer
The ISL8700, ISL8701, ISL8702 family of ICs provide four
delay adjustable sequenced outputs while monitoring an
input voltage all with a minimum of external components.
High performance DSP, FPGA, µP and various subsystems
require input power sequencing for proper functionality at
initial power-up and the ISL870x provides this function while
monitoring the distributed voltage for over and undervoltage
compliance.
The ISL8700 and ISL8701 operate over the +2.5V to +24V
nominal voltage range, whereas the ISL8702 operates over
the +2.5V to +12V nominal voltage range. All three have a
user adjustable time from UV and OV voltage compliance to
sequencing start via an external capacitor when in auto start
mode and adjustable time delay to subsequent ENABLE
output signal via external resistors.
Additionally, the ISL8702 provides an input for sequencing
on and off operation (SEQ_EN) and for voltage window
compliance reporting (FAULT) over the +2.5V to +12V
voltage range.
Easily daisy chained for more than 4 sequenced signals.
Altogether, the ISL870x provides these adjustable features
with a minimum of external BOM. See Figure 1 for typical
implementation.
Ordering Information
PART NUMBER PART
TEMP. PACKAGE PKG.
(Note)
MARKING RANGE (°C) (Pb-free) DWG. #
ISL8700IBZ* ISL 8700IBZ -40 to +85 14 Ld SOIC M14.15
ISL8701IBZ* ISL 8701IBZ -40 to +85 14 Ld SOIC M14.15
ISL8702IBZ* ISL 8702IBZ -40 to +85 14 Ld SOIC M14.15
ISL870xEVAL1 Evaluation Platform
*Add “-T” suffix for tape and reel. Please refer to TB347 for details
on reel specifications.
NOTE: These Intersil Pb-free plastic packaged products employ
special Pb-free material sets; molding compounds/die attach
materials and 100% matte tin plate PLUS ANNEAL - e3 termination
finish, which is RoHS compliant and compatible with both SnPb and
Pb-free soldering operations. Intersil Pb-free products are MSL
classified at Pb-free peak reflow temperatures that meet or exceed
the Pb-free requirements of IPC/JEDEC J STD-020.
Features
• Adjustable Delay to Subsequent Enable Signal
• Adjustable Delay to Sequence Auto Start
• Adjustable Distributed Voltage Monitoring
• Undervoltage and Overvoltage Adjustable Delay to Auto
Start Sequence
• I/O Options
ENABLE (ISL8700, ISL8702) and ENABLE# (ISL8701)
SEQ_EN (ISL8702)
• Voltage Compliance Fault Output
• Pb-Free (RoHS Compliant)
Applications
• Power Supply Sequencing
• System Timing Function
2.5V TO 24V (2.5V TO 12V FOR ISL8702)
Ru VIN ENABLE_A
SEQ_EN*
ENABLE_B
ENABLE_C
UV ENABLE_D
Rm
OV
FAULT*
GND TB TC TD TIME
Rl
EN
DC/DC
Vo1
EN
DC/DC
Vo2
EN
DC/DC
Vo3
EN
DC/DC
Vo4
* SEQ_EN and FAULT are not available on ISL8700 and ISL8701
FIGURE 1. ISL870x IMPLEMENTATION
1 CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2006, 2008. All Rights Reserved
All other trademarks mentioned are the property of their respective owners.

1 Page





ISL8700 pdf, ピン配列
ISL8700, ISL8701, ISL8702
Absolute Maximum Ratings
ISL8700, ISL8701 VIN, ENABLE(#), FAULT . . . . . . . . 27V, to -0.3V
ISL8702 VIN, ENABLE(#), FAULT . . . . . . . . . . . . . . . . 14V, to -0.3V
TIME, TB, TC, TD, UV, OV . . . . . . . . . . . . . . . . . . . . . +6V, to -0.3V
SEQ_EN(#) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . VIN+0.3V, to -0.3V
ENABLE, ENABLE # Output Current . . . . . . . . . . . . . . . . . . . 10mA
Operating Conditions
Temperature Range . . . . . . . . . . . . . . . . . . . . . . . . . .-40°C to +85°C
Supply Voltage Range (Nominal). . . . . . . . . . . . . . . . . . 2.5V to 24V
ISL8702 Supply Voltage Range (Nominal) . . . . . . . . . . 2.5V to 12V
Thermal Information
Thermal Resistance (Typical, Note 1)
θJA (°C/W)
14 Ld SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
110
Maximum Junction Temperature (Plastic Package) . . . . . . . +125°C
Maximum Storage Temperature Range . . . . . . . . . .-65°C to +150°C
Pb-free Reflow Profile . . . . . . . . . . . . . . . . . . . . . . . . .see link below
http://www.intersil.com/pbfree/Pb-FreeReflow.asp
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and
result in failures not covered by warranty.
NOTE:
1. θJA is measured with the component mounted on a high effective thermal conductivity test board in free air. See Tech Brief TB379 for details.
Electrical Specifications
PARAMETER
Nominal VIN = 2.5V to +24V, TA = TJ = -40°C to +85°C, Unless Otherwise Specified.
ISL8702 VIN = 2.5V to +12V
SYMBOL
TEST CONDITIONS
MIN TYP
UV AND OV INPUTS
UV/OV Rising Threshold
UV/OV Falling Threshold
UV/OV Hysteresis
UV/OV Input Current
TIME, ENABLE/ENABLE# OUTPUTS
VUVRvth
VUVFvth
VUVhys
IUV
VUVRvth - VUVFvth
1.16
1.06
-
-
1.21
1.10
104
10
TIME Pin Charging Current
TIME Pin Threshold
Time from VIN Valid to ENABLE_A
Time from VIN Invalid to Shutdown
ENABLE Output Resistance
ITIME
VTIME_VTH
tVINSEQpd SEQ_EN = high, CTIME = open
tVINSEQpd_10 SEQ_EN = high, CTIME = 10nF
tVINSEQpd500 SEQ_EN = high, CTIME = 500nF
tshutdown UV or OV to simultaneous shutdown
REN
IENABLE = 1mA
- 2.6
1.9 2.0
- 30
- 7.7
- 435
--
- 100
ENABLE Output Low
ENABLE Pull-Down Current
Delay to Subsequent ENABLE Turn-On/Off
SEQUENCE ENABLE AND FAULT I/O
Vol
Ipulld
tdel_120
tdel_3
tdel_0
IENABLE = 1mA
ENABLE = 1V
RTX = 120kΩ
RTX = 3kΩ
RTX = 0Ω
- 0.1
10 15
155 195
3.5 4.7
- 0.5
VIN Valid to FAULT Low
VIN Invalid to FAULT High
FAULT Pull-down Current
tFLTL
tFLTH
FAULT = 1V
15 30
- 0.5
10 15
SEQ_EN Pull-up Voltage
SEQ_EN Low Threshold Voltage
SEQ_EN High Threshold Voltage
Delay to ENABLE_A Deasserted
VSEQ
SEQ_EN open
VilSEQ_EN
VihSEQ_EN
tSEQ_EN_ENA SEQ_EN low to ENABLE_A low
- VIN
--
1.2 -
- 0.2
MAX
1.28
1.18
-
-
-
2.25
-
-
-
1
-
-
-
240
6
-
50
-
-
-
0.3
-
1
UNIT
V
V
mV
nA
µA
V
µs
ms
ms
µs
Ω
V
mA
ms
ms
ms
µs
µs
mA
V
V
V
µs
3 FN9250.2
March 21, 2008


3Pages


ISL8700 電子部品, 半導体
ISL8700, ISL8701, ISL8702
On the ISL8702, enabling of on or off sequencing can also be
signaled via the SEQ_EN input pin once voltage compliance is
met. Initially the SEQ_EN pin should be held low and released
when sequence start is desired. The on sequence of the
ENABLE outputs is as previously described. The off sequence
feature is only available on the variants having the SEQ_EN or
the SEQ_EN# inputs, this being the ISL8702. The sequence is
D off, then C off, then B off and finally A off. Once SEQ_EN
(SEQ_EN#) is signaled low (high) the TIME cap is charged to
2V once again. Once this Vth is reached ENABLE_D
transitions to its reset state and CTIM is discharged. A delay
and subsequent sequence off is then determined by TD resistor
to ENABLE_C. Likewise, a delay to ENABLE_B and then
ENABLE_A turn-off is determined by TC and TB resistor values
respectively.
With the ISL8700, ISL8701, a quasi down sequencing of the
ENABLE outputs can be achieved by loading the ENABLE pins
with various value capacitors to ground. When a simultaneous
output latch off is invoked, the caps will set the falling ramp of
the various ENABLE outputs thus adjusting the time to Vth for
various DC/DC convertors or other circuitry.
Regardless of IC variant, the FAULT signal is always valid at
operational voltages and can be used as justification for
SEQ_EN release or even controlled with an RC timer for
sequence on.
Programming the Undervoltage and Overvoltage
Limits
When choosing resistors for the divider, remember to keep the
current through the string bounded by power loss at the top end
and noise immunity at the bottom end. For most applications,
total divider resistance in the 10kΩ to 1000kΩ range is
advisable with high precision resistors being used to reduce
monitoring error. Although for the ISL870x two dividers of two
resistors each can be employed to separately monitor the OV
and UV levels for the VIN voltage which will be discussed here
using a single three resistor string for monitoring the VIN
voltage, referencing Figure 1. In the three resistor divider string
with Ru (upper), Rm (middle) and Rl (lower), the ratios of each
in combination to the other two is balanced to achieve the
desired UV and OV trip levels. Although this IC has a bias
range of 2.5V to 24V (12V for ISL8702), it can monitor any
voltage >1.22V.
The ratio of the desired overvoltage trip point to the internal
reference is equal to the ratio of the two upper resistors to the
lowest (ground connected) resistor.
The ratio of the desired undervoltage trip point to the internal
reference voltage is equal to the ratio of the uppermost (voltage
connected) resistor to the lower two resistors.
These assumptions are true for both rising (turn-on) or falling
(shutdown) voltages.
The following is a practical example worked out. For detailed
equations on how to perform this operation for a given supply
requirement, please refer to the next section.
1. Determine if turn-on or shutdown limits are preferred and
in this example we will determine the resistor values
based on the shutdown limits.
2. Establish lower and upper trip level: 12V ±10% or 13.2V
(OV) and 10.8V (UV)
3. Establish total resistor string value: 100kΩ, Ir = divider
current
4. (Rm + Rl) x Ir = 1.1V @ UV and Rl x Ir = 1.2V @ OV
5. Rm + Rl = 1.1V/Ir @ UV = Rm + Rl = 1.1V/(10.8V/100kΩ)
= 10.370kΩ
6. Rl = 1.2V/Ir @ OV = Rl = 1.2V/(13.2V/100kΩ) = 9.242kΩ
7. Rm = 10.370kΩ - 9.242kΩ = 1.128kΩ
8. Ru = 100kΩ - 10.370kΩ = 89.630kΩ
9. Choose standard value resistors that most closely
approximate these ideal values. Choosing a different total
divider resistance value may yield a more ideal ratio with
available resistors values.
In our example with the closest standard values of
Ru = 90.9kΩ, Rm = 1.13kΩ and Rl = 9.31kΩ, the nominal UV
falling and OV rising will be at 10.9V and 13.3V respectively.
An Advanced Tutorial on Setting UV and OV
Levels
This section discusses in additional detail the nuances of
setting the UV and OV levels, providing more insight into the
ISL870x than the earlier text.
The following equation set can alternatively be used to work
out ideal values for a 3 resistor divider string of Ru, Rm and
Rl. These equations assume that VREF is the center point
between VUVRvth and VUVFvth (i.e. (VUVRvth + VUVFvth)/2
= 1.17V), Iload is the load current in the resistor string
(i.e. VIN /(Ru + Rm + Rl)), VIN is the nominal input voltage
and Vtol is the acceptable voltage tolerance, such that the
UV and OV thresholds are centered at VIN ± Vtol. The actual
acceptable voltage window will also be affected by the
hysteresis at the UV and OV pins. This hysteresis is
amplified by the resistor string such that the hysteresis at the
top of the string is calculated in Equation 1:
Vhys = VUVhys × VOUT VREF
(EQ. 1)
This means that the VIN ± Vtol thresholds will exhibit
hysteresis resulting in thresholds of VIN + Vtol ± Vhys/2 and
VIN - Vtol ± Vhys/2.
There is a window between the VIN rising UV threshold and
the VIN falling OV threshold where the input level is
guaranteed not to be detected as a fault. This window exists
between the limits VIN ± (Vtol - Vhys/2). There is an
extension of this window in each direction up to
VIN ± (Vtol + Vhys/2), where the voltage may or may not be
6 FN9250.2
March 21, 2008

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共有リンク

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部品番号部品説明メーカ
ISL8700

Adjustable Quad Sequencer

Intersil
Intersil
ISL8700A

(ISL8700A - ISL8705A) Adjustable Quad Sequencer

Intersil Corporation
Intersil Corporation
ISL8701

Adjustable Quad Sequencer

Intersil
Intersil
ISL8701A

(ISL8700A - ISL8705A) Adjustable Quad Sequencer

Intersil Corporation
Intersil Corporation


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