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PDF ISL6416 Data sheet ( Hoja de datos )
| Número de pieza | ISL6416 | |
| Descripción | Low-Noise LDO Regulator | |
| Fabricantes | Intersil | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ISL6416 (archivo pdf) en la parte inferior de esta página. Total 10 Páginas | ||
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ISL6416
FN9193.0
Triple Output, Low-Noise LDO Regulator
with Integrated Reset Circuit
The ISL6416 is an ultra low noise triple output LDO regulator
with microprocessor reset circuit and is optimized for
powering wireless chip sets. The IC accepts an input voltage
range of 3.0V to 3.6V and provides three regulated output
voltages: 1.8V (LDO1), 2.8V (LDO2), and another ultra-clean
2.8V (LDO3). On chip logic provides sequencing between
LDO1 and LDO2 for the BBP/MAC and the I/O supply
voltage outputs. LDO3 features ultra low noise that does not
exceed 30µVRMS (typical) to aid VCO stability. High
integration makes the ISL6416 an ideal choice to power
many of today’s small form factor industry standard wireless
cards such as PCMCIA, mini-PCI and Cardbus-32.
The ISL6416 uses an internal PMOS transistor as the pass
device. The ISL6416 also integrates a reset function, which
eliminates the need for the additional reset IC required in
WLAN applications. The IC asserts a RESET signal
whenever the VIN supply voltage drops below a preset
threshold, keeping it asserted for at least 25ms after Vin has
risen above the reset threshold. FAULT indicates the loss of
regulation on LDO1.
Ordering Information
TEMP.
PART NUMBER RANGE (°C) PACKAGE
PKG.
DWG. #
ISL6416IA
-40 to +85 16 Ld QSOP M16.15A
ISL6416IAZ (Note 1) -40 to +85 16 Ld QSOP M16.15A
(Pb-free)
NOTES:
1. Tape and Reel available. Add “-T” suffix for Tape and Reel
Packing Option.
2. Intersil Pb-free products employ special Pb-free material sets;
molding compounds/die attach materials and 100% matte tin
plate termination finish, which are RoHS compliant and
compatible with both SnPb and Pb-free soldering operations.
Intersil Pb-free products are MSL classified at Pb-free peak
reflow temperatures that meet or exceed the Pb-free
requirements of IPC/JEDEC J STD-020C.
Features
• Three LDOs and a RESET circuit
• High Output Current
- LDO1, 1.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330mA
- LDO2, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225mA
- LDO3, 2.8V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125mA
• Low Output Voltage Noise
- <30µVRMS (typical) for LDO3 (VCO Supply)
• Stable with Small Ceramic Output Capacitors
• Extensive Protection and Monitoring Features
- Overcurrent protection
- Short circuit protection
- Thermal shutdown
- FAULT indicator
• Logic-Controlled Shutdown Pin
• Integrated Microprocessor Reset Circuit
- Programmable Reset Delay
• Proven Reference Design for a Total WLAN System
Solution
• Pb-Free Available (RoHS Compliant)
Applications
• WLAN Cards
- PCMCIA, Cardbus32, MiniPCI Cards
- Compact Flash Cards
• Hand-Held Instruments
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Intersil (and design) is a registered trademark of Intersil Americas Inc.
Copyright © Intersil Americas Inc. 2004. All Rights Reserved. All Rights Reserved.
All other trademarks mentioned are the property of their respective owners.
1 page  
ISL6416
Electrical Specifications VIN = +3.3V, Compensation Capacitor = 33nF, TA = 25°C, unless otherwise noted. (Continued)
PARAMETER
TEST CONDITIONS
MIN TYP MAX
Output Voltage Noise (Note 6)
LDO3 SPECIFICATIONS
10Hz < f < 100kHz, IOUT = 10mA
COUT = 2.2F
- 65 -
COUT = 10F
- 60 -
Output Voltage (VOUT3)
Output Voltage Accuracy
Maximum Output Current (IOUT3)
Output Current Limit
- 2.8 -
IOUT = 10mA, TA = -40°C to 85°C
-2.0
-
2.0
VIN = 3.3V
125 -
-
300 -
-
Dropout Voltage (Note 4)
Line Regulation
Load Regulation
Output Voltage Noise (Note 6)
RESET BLOCK SPECIFICATIONS
IOUT = 125mA
- 65 200
VIN = 3.0V to 3.6V, IOUT = 10mA
-0.15
0.0
0.15
IOUT = 10mA to 125mA
-1.0 0.2 1.0
10Hz < f < 100kHz, IOUT = 10mA
COUT = 2.2F
- 30 -
COUT = 10F
- 20 -
Reset Threshold
2.564
2.630
2.66
Reset Threshold Hysteresis (Note 5)
6.3 -
-
VIN to Reset Delay (Note 5)
RESET Active Timeout Period (Note 5)
VCC = VTH to VTH - 100mV
CT = 0.01µF
- 20
50 -
-
-
FAULT
Rising Threshold
% of VOUT
+5.5 +8.0 +10.5
Falling Threshold
% of VOUT
-10.5
-8.0
-5.5
4. The dropout voltage is defined as VIN - VOUT, when VOUT is 50mV below the value of VOUT for VIN = VOUT + 0.5V.
5. The RESET time is linear with CT at a slope of ~5ms/nF. Thus, at 10nF (0.01F) the RESET time is 50ms.
6. Guaranteed by design, not production tested.
UNITS
VRMS
VRMS
V
%
mA
mA
mV
%/V
%
VRMS
VRMS
V
mV
s
ms
%
%
Typical Performance Curves
The test conditions for the Typical Operating Performance are: VIN = 3.3V, TA = 25°C,
Unless Otherwise Noted
SHDN
1V/DIV
VOUT3
1V/DIV
VOUT2
1V/DIV
VOUT1
1V/DIV
100µs/DIV
FIGURE 1. START-UP SEQUENCE
5
SHDN
1V/DIV
VOUT1
1V/DIV
100µs/DIV
VOUT2
1V/DIV
VOUT3
1V/DIV
FIGURE 2. SHUTDOWN SEQUENCE
FN9193.0
November 3, 2004
5 Page | ||
| Páginas | Total 10 Páginas | |
| PDF Descargar | [ Datasheet ISL6416.PDF ] | |
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