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PDF SP3483 Data sheet ( Hoja de datos )
| Número de pieza | SP3483 | |
| Descripción | +3.3V Low Power Slew Rate Limited Half-Duplex RS-485 Transceiver | |
| Fabricantes | Exar | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de SP3483 (archivo pdf) en la parte inferior de esta página. Total 9 Páginas | ||
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SP3483
+3.3V Low Power Slew Rate Limited
Half-Duplex RS-485 Transceiver
• RS-485 and RS-422 Transceiver
• Operates from a single +3.3V Supply
• Interoperable with +5.0V logic
• Driver/Receiver Enable
• Low Power Shutdown mode
• -7V to +12V Common-Mode Input Voltage Range
• Allows up to 32 transceivers on the serial bus
• Compatibility with the industry standard
75176 pinout
• Driver Output Short-Circuit Protection
• Slew Rate Limited Driver for Low EMI
DESCRIPTION
The SP3483 device is part of a family of +3.3V low power half-duplex transceivers that meet
the specifications of the RS-485 and RS-422 serial protocols. This device is pin-to-pin compat-
ible with the Exar SP483 device as well as popular industry standards. The SP3483 features
Exar's BiCMOS design allowing low power operation without sacrificing performance. The
SP3483 is slew rate limited to reduce EMI and can meet the requirements of the RS-485
and RS-422 protocols up to 250kbps.
INPUTS
RE DE DI
X 11
X 10
X 0X
LINE
CONDITION
No Fault
No Fault
X
OUTPUTS
BA
01
10
ZZ
Table 1. Transmit Function Truth Table
TRUTH TABLES
INPUTS
RE DE
00
00
00
10
A-B
+0.2V
-0.2V
Inputs Open
X
OUTPUTS
R
1
0
1
Z
Table 2. Receive Function Truth Table
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP3483_100_010912
1 page  
D
Vcc
VOD
R
R VOC
Figure 1. Driver DC Test Load Circuit
Test Circuits
VDM
GENERATOR
(NOTE 1)
D
50Ω
VCC
S1
R L = 27Ω
OUT
C L = 15pF
(NOTE 2)
VOM =
VOH + VOL
2
≈ 1.5V
Figure 2. Driver Propagation Delay Test Circuit
GENERATOR
(NOTE 1)
D
50Ω
VCC
CL
RL = OUT
60Ω
C L= 15pF (NOTE 2)
Figure 3. Driver Differential Output Delay and
Transition Time Circuit.
0V OR 3V
D
S1
GENERATOR
(NOTE 1)
50Ω
C L = 50pF
(NOTE 2)
VCC
R L = 110Ω
OUT
Figure 5. Driver Enable and Disable Timing Circuit,
Output Low
1.5V S3
-1.5V VID R
GENERATOR
(NOTE 1)
50Ω
1k
CL= 15pF
(NOTE 2)
S1
VCC
S2
GENERATOR
(NOTE 1)
S1
D
50Ω
CL = 50pF
(NOTE 2)
OUT
RL = 110Ω
VOM =
VOH + VOL
2
≈ 1.5V
Figure 4. Driver Enable and Disable Timing Circuit,
Output High
GENERATOR
(NOTE 1)
V ID R
50Ω
OUT
CL = 15pF
(NOTE 2)
1.5V
0V
VOM = VCC
2
Figure 6. Receiver Propagation Delay Test Circuit
DE = 0 or Vcc
A/Y
DI = 0 or Vcc
D
B/Z
IOSD
100Ω
-7V to +12V V
Figure 7. Receiver Enable and Disable Timing
Circuit
Figure 8. Driver Short Circuit Current Limit Test
Exar Corporation 48720 Kato Road, Fremont CA, 94538 • 510-668-7017 • www.exar.com
SP3483_100_010912
5 Page | ||
| Páginas | Total 9 Páginas | |
| PDF Descargar | [ Datasheet SP3483.PDF ] | |
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