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CY14B101MA の電気的特性と機能

CY14B101MAのメーカーはCypress Semiconductorです、この部品の機能は「1-Mbit (128K x 8/64K x 16) nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14B101MA
部品説明 1-Mbit (128K x 8/64K x 16) nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14B101MA Datasheet, CY14B101MA PDF,ピン配置, 機能
CY14B101KA
CY14B101MA
1-Mbit (128K × 8/64K × 16) nvSRAM with
Real Time Clock
1-Mbit (128K × 8/64K × 16) nvSRAM with Real Time Clock
Features
1-Mbit nonvolatile static random access memory (nvSRAM)
25 ns and 45 ns access times
Internally organized as 128K × 8 (CY14B101KA) or 64K × 16
(CY14B101MA)
Hands off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements is initiated by
software, hardware, or AutoStore on power-down
RECALL to SRAM initiated on power-up or by software
High reliability
Infinite Read, Write, and RECALL cycles
1 million STORE cycles to QuantumTrap
20 year data retention
Real time clock (RTC)
Full featured real time clock
Watchdog timer
Clock alarm with programmable interrupts
Capacitor or battery backup for RTC
Backup current of 0.35 µA (Typ)
Industry standard configurations
Single 3 V +20%, –10% operation
Industrial temperature
Packages
44-/54-pin thin small outline package (TSOP) Type II
48-pin shrink small outline package (SSOP)
Pb-free and restriction of hazardous substances (RoHS)
compliant
Functional Description
The Cypress CY14B101KA/CY14B101MA combines a 1-Mbit
nvSRAM with a full featured real time clock in a monolithic
integrated circuit. The embedded nonvolatile elements
incorporate QuantumTrap technology producing the world’s
most reliable nonvolatile memory. The SRAM is read and written
an infinite number of times, while independent nonvolatile data
resides in the nonvolatile elements.
The real time clock function provides an accurate clock with leap
year tracking and a programmable, high accuracy oscillator. The
alarm function is programmable for periodic minutes, hours,
days, or months alarms. There is also a programmable watchdog
timer for process control.
For a complete list of related documentation, click here.
Logic Block Diagram[1, 2, 3]
A5
A6
A7
A8
A9
A12
A13
A14
A15
A16
R
O
W
D
E
C
O
D
E
R
Quatrum
Trap
1024 X 1024
STORE
RECALL
STATIC RAM
ARRAY
1024 X 1024
VCC
VCA
P
POWER
CONTROL
STORE/RECALL
CONTROL
SOFTWARE
DETECT
VRTCbat
VRTCcap
HSB
A14 - A2
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
I
N
P
U
T
B COLUMN I/O
U
F
F
E
R COLUMN DEC
S
A0 A1 A2 A3 A4 A10 A11
RTC
MUX
Xout
Xin
INT
A16- A0
OE
WE
CE
BLE
BHE
Notes
1. Address A0–A16 for × 8 configuration and Address A0–A15 for × 16 configuration.
2. Data DQ0–DQ7 for × 8 configuration and Data DQ0–DQ15 for × 16 configuration.
3. BHE and BLE are applicable for × 16 configuration only.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-42880 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised February 22, 2016

1 Page





CY14B101MA pdf, ピン配列
CY14B101KA
CY14B101MA
Pinouts
Figure 1. Pin Diagram – 44-pin, 54-pin TSOP II, and 48-pin SSOP
INT
NC[7]
A0
A1
A2
A3
A4
CE
DQ0
DQ1
VCC
VSS
DQ2
DQ3
WE
A5
A6
A7
A8
A9
Xout
Xin
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 44-pin TSOP II 36
10 (× 8)
35
11 Top View 34
12 (not to scale) 33
13 32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
HSB
NC[6]
NNCC[[54]]
NC
A16
A15
OE
DQ7
DQ6
VSS
VCC
DQ5
DQ4
VCAP
A14
A13
A12
A11
A10
VRTCcap
VRTCbat
VCAP
A16
A14
A12
A7
A6
A5
INT
A4
NC
NC
NC
VSS
NC
VRTCbat
DQ0
A3
A2
A1
A0
DQ1
DQ2
Xout
Xin
1 48
2 47
3 46
4 45
5 44
6 43
7 42
8 41
9 48-pin SSOP 40
10 (× 8) 39
11 Top View
12
13
(not to scale)
38
37
36
14 35
15 34
16 33
17 32
18 31
19 30
20 29
21 28
22 27
23 26
24 25
VCC
A15
HSB
WE
A13
A8
A9
NC
A11
NC
NC
NC
VSS
NC
VRTCcap
DQ6
OE
A10
CE
DQ7
DQ5
DQ4
DQ3
VCC
NIN[7CT]
A0
A1
A2
A3
A4
CE
DQ0
DQ1
DQ2
DQ3
VCC
VSS
DQ4
DQ5
DQ6
DQ7
WE
A5
A6
A7
A8
A9
NC
Xout
Xin
1 54
2 53
3 52
4 51
5 50
6 49
7 48
8 47
9
10
54-pin TSOP II
46
45
11 (× 16)
12
13
Top View
44
43
42
14 (not to scale) 41
15 40
16 39
17 38
18 37
19
20
36
35
21 34
22 33
23 32
24 31
25 30
26 29
27 28
HNNNSCCCB[[[645]]]
A15
OE
BHE
BLE
DQ15
DQ14
DQ13
DQ12
VSS
VCC
DQ 11
DQ 10
DQ9
DQ 8
VCAP
A14
A13
A12
A11
A10
NC
VRTCcap
VRTCbat
Notes
4. Address expansion for 2-Mbit. NC pin not connected to die.
5. Address expansion for 4-Mbit. NC pin not connected to die.
6. Address expansion for 8-Mbit. NC pin not connected to die.
7. Address expansion for 16-Mbit. NC pin not connected to die.
Document Number: 001-42880 Rev. *O
Page 3 of 37


3Pages


CY14B101MA 電子部品, 半導体
CY14B101KA
CY14B101MA
SRAM write operations that are in progress when HSB is driven
LOW by any means are given time (tDELAY) to complete before
the STORE operation is initiated. However, any SRAM write
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB is not driven
LOW by the CY14B101KA/CY14B101MA. But any SRAM read
and write cycles are inhibited until HSB is returned HIGH by MPU
or other external source.
During any STORE operation, regardless of how it is initiated,
the CY14B101KA/CY14B101MA continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
completion of the STORE operation, the nvSRAM memory
access is inhibited for tLZHSB time after HSB pin returns HIGH.
Leave the HSB unconnected if it is not used.
Hardware RECALL (Power-Up)
During power-up or after any low power condition
(VCC< VSWITCH), an internal RECALL request is latched. When
VCC again exceeds the VSWITCH on power-up, a RECALL cycle
is automatically initiated and takes tHRECALL to complete. During
this time, the HSB pin is driven LOW by the HSB driver and all
reads and writes to nvSRAM are inhibited.
Software STORE
Data is transferred from the SRAM to the nonvolatile memory by
a software address sequence. The CY14B101KA/CY14B101MA
Software STORE cycle is initiated by executing sequential CE or
OE controlled read cycles from six specific address locations in
exact order. During the STORE cycle, an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
Because a sequence of reads from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
To initiate the Software STORE cycle, the following read
sequence must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8FC0 Initiate STORE cycle
The software sequence may be clocked with CE controlled reads
or OE controlled reads, with WE kept HIGH for all the six READ
sequences. After the sixth address in the sequence is entered,
the STORE cycle commences and the chip is disabled. HSB is
driven LOW. After the tSTORE cycle time is fulfilled, the SRAM is
activated again for the read and write operation.
Software RECALL
Data is transferred from the nonvolatile memory to the SRAM by
a software address sequence. A Software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the Software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE or OE controlled read operations
must be performed:
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4C63 Initiate RECALL cycle
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared. Next, the nonvolatile information is transferred into the
SRAM cells. After the tRECALL cycle time, the SRAM is again
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
Document Number: 001-42880 Rev. *O
Page 6 of 37

6 Page



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部品番号部品説明メーカ
CY14B101MA

1-Mbit (128K x 8/64K x 16) nvSRAM

Cypress Semiconductor
Cypress Semiconductor


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