DataSheet.jp

CY14E256Q の電気的特性と機能

CY14E256QのメーカーはCypress Semiconductorです、この部品の機能は「256-Kbit (32 K x 8) SPI nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14E256Q
部品説明 256-Kbit (32 K x 8) SPI nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




このページの下部にプレビューとCY14E256Qダウンロード(pdfファイル)リンクがあります。

Total 30 pages

No Preview Available !

CY14E256Q Datasheet, CY14E256Q PDF,ピン配置, 機能
CY14C256Q
CY14B256Q
CY14E256Q
256-Kbit (32 K × 8) SPI nvSRAM
256-Kbit (32 K × 8) SPI nvSRAM
Features
256-Kbit nonvolatile static random access memory (nvSRAM)
internally organized as 32 K × 8
STORE to QuantumTrap nonvolatile elements initiated
automatically on power-down (AutoStore) or by using SPI
instruction (Software STORE) or HSB pin (Hardware
STORE)
RECALL to SRAM initiated on power-up (Power-Up
RECALL) or by SPI instruction (Software RECALL)
Support automatic STORE on power-down with a small
capacitor (except for CY14X256Q1A)
High reliability
Infinite read, write, and RECALL cycles
1million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
40 MHz and 104 MHz High speed serial peripheral interface
(SPI)
40 MHz clock rate SPI write and read with zero cycle delay
104 MHz clock rate SPI write and SPI read (with special fast
read instructions)
Supports SPI mode 0 (0,0) and mode 3 (1,1)
SPI access to special functions
Nonvolatile STORE/RECALL
8-byte serial number
Manufacturer ID and Product ID
Sleep mode
Write protection
Hardware protection using Write Protect (WP) pin
Software protection using Write Disable instruction
Software block protection for 1/4, 1/2, or entire array
Low power consumption
Average active current of 3 mA at 40 MHz operation
Average standby mode current of 150 A
Sleep mode current of 8 A
Logic Block Diagram
VCC VCAP
Industry standard configurations
Operating voltages:
• CY14C256Q: VCC = 2.4 V to 2.6 V
• CY14B256Q: VCC = 2.7 V to 3.6 V
• CY14E256Q: VCC = 4.5 V to 5.5 V
Industrial temperature
8- and 16-pin small outline integrated circuit (SOIC) package
Restriction of hazardous substances (RoHS) compliant
Functional Overview
The Cypress CY14X256Q combines a 256-Kbit nvSRAM[1] with
a nonvolatile element in each memory cell with serial SPI
interface. The memory is organized as 32 K words of 8 bits each.
The embedded nonvolatile elements incorporate the
QuantumTrap technology, creating the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while the QuantumTrap cells provide highly reliable
nonvolatile storage of data. Data transfers from SRAM to the
nonvolatile elements (STORE operation) takes place
automatically at power-down (except for CY14X256Q1A). On
power-up, data is restored to the SRAM from the nonvolatile
memory (RECALL operation). You can also initiate the STORE
and RECALL operations through SPI instruction.
For a complete list of related documentation, click here.
Configuration
Feature
AutoStore
Software
STORE
Hardware
STORE
CY14X256Q1A CY14X256Q2A CY14X256Q3A
No Yes Yes
Yes Yes Yes
No No Yes
Serial Number
8x8
SI
CS
SCK
WP
SO
Power Control
Block
SLEEP
SPI Control Logic
Write Protection
Instruction decoder
Manufacturer ID /
Product ID
RDSN/WRSN/RDID
READ/WRITE
STORE/RECALL/ASENB/ASDISB
Memory
Data &
Address
Control
QuantumTrap
32 K x 8
SRAM
32 K x 8
STORE
RECALL
WRSR/RDSR/WREN
Status Register
Note
1. This device will be referred to as nvSRAM throughout the document.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-65282 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 12, 2014

1 Page





CY14E256Q pdf, ピン配列
CY14C256Q
CY14B256Q
CY14E256Q
Pinouts
CS
SO
WP
VSS
18
2 CY14X256Q1A 7
3
Top View
not to scale
6
45
Figure 1. 8-pin SOIC pinout [2, 3, 4]
VCC
HOLD
SCK
SI
CS
SO
VCAP
VSS
18
2 CY14X256Q2A 7
3
Top View
not to scale
6
45
VCC
HOLD
SCK
SI
Figure 2. 16-pin SOIC pinout
NC
NC
NC
NC
WP
HOLD
NC
VSS
1 16
2 15
3 CY14X256Q3A 14
Top View
4 not to scale 13
5 12
6 11
7 10
89
VCC
NC
VCAP
SO
SI
SCK
CS
HSB
Pin Definitions
Pin Name [2, 3, 4] I/O Type
Description
CS Input Chip Select. Activates the device when pulled LOW. Driving this pin high puts the device in low
power standby mode.
SCK
Input
Serial
of this
Clock. Runs
clock. Serial
at speeds up to
output is driven
a
at
maximum
the falling
oefdfgSeCKo.f
Serial input
the clock.
is
latched
at
the
rising
edge
SI Input Serial Input. Pin for input of all SPI instructions and data.
SO Output Serial Output. Pin for output of data through SPI.
WP Input Write Protect. Implements hardware write protection in SPI.
HOLD
Input HOLD Pin. Suspends serial operation.
HSB
Input/Output Hardware STORE Busy:
Output: Indicates busy status of nvSRAM when LOW. After each Hardware and Software STORE
operation HSB
a weak internal
is driven HIGH
pull-up resistor
for a short
keeps this
ptiimneH(ItGHHHH(DE)xwteirtnhasltpaunldl-aurpdroeustisptuotrhciognhnceucrtrieonntoapntdiotnhael)n.
Input: Hardware STORE implemented by pulling this pin LOW externally.
VCAP
Power supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to STORE data from the
SRAM to nonvolatile elements. If AutoStore is not needed, this pin must be left as No Connect. It
must never be connected to ground.
NC No connect No Connect: This pin is not connected to the die.
VSS Power supply Ground
VCC Power supply Power supply
Notes
2. HSB pin is not available in 8-pin SOIC packages (CY14X256Q1A/CY14X256Q2A).
3. CY14X256Q1A part does not have VCAP pin and does not support AutoStore.
4. CY14X256Q2A part does not have WP pin.
Document Number: 001-65282 Rev. *I
Page 3 of 33


3Pages


CY14E256Q 電子部品, 半導体
CY14C256Q
CY14B256Q
CY14E256Q
controller must provide sufficient delay for the RECALL operation
to complete before issuing any memory access instructions.
Disabling and Enabling AutoStore
If the application does not require the AutoStore feature, it can
be disabled by using the ASDISB instruction. If this is done, the
nvSRAM does not perform a STORE operation at power-down.
AutoStore can be re-enabled by using the ASENB instruction.
However, these operations are not nonvolatile and if you need
this setting to survive the power cycle, a STORE operation must
be performed following AutoStore Disable or Enable operation.
Note CY14X256Q2A/CY14X256Q3A comes from the factory
with AutoStore enabled and
CY14X256Q1A/CY14X256Q2A/CY14X256Q3A comes from the
factory with 0x00 written in all cells. In CY14X256Q1A, VCAP pin
is not present and AutoStore option is not available. The
AutoStore Enable and Disable instructions to CY14X256Q1A are
ignored.
Note If AutoStore is disabled and VCAP is not required, then the
VCAP pin must be left open. The VCAP pin must never be
connected to ground. The Power-Up RECALL operation cannot
be disabled in any case.
Serial Peripheral Interface
SPI Overview
The SPI is a four-pin interface with Chip Select (CS), Serial Input
(SI), Serial Output (SO), and Serial Clock (SCK) pins.
CY14X256Q provides serial access to nvSRAM through SPI
interface. The SPI bus on CY14X256Q can run at speeds up to
104 MHz except READ instruction.
The SPI is a synchronous serial interface which uses clock and
data pins for memory access and supports multiple devices on
the data bus. A device on SPI bus is activated using the CS pin.
The relationship between chip select, clock, and data is dictated
by the SPI mode. This device supports SPI modes 0 and 3. In
both these modes, data is clocked into the nvSRAM on the rising
edge of SCK starting from the first rising edge after CS goes
active.
The SPI protocol is controlled by opcodes. These opcodes
specify the commands from the bus master to the slave device.
After CS is activated the first byte transferred from the bus
master is the opcode. Following the opcode, any addresses and
data are then transferred. The CS must go inactive after an
operation is complete and before a new opcode can be issued.
The commonly used terms used in SPI protocol are given below:
SPI Master
The SPI master device controls the operations on a SPI bus. A
SPI bus may have only one master with one or more slave
devices. All the slaves share the same SPI bus lines and the
master may select any of the slave devices using the CS pin. All
the operations must be initiated by the master activating a slave
device by pulling the CS pin of the slave LOW. The master also
generates the SCK and all the data transmission on SI and SO
lines are synchronized with this clock.
SPI Slave
The SPI slave device is activated by the master through the Chip
Select line. A slave device gets the SCK as an input from the SPI
master and all the communication is synchronized with this
clock. SPI slave never initiates a communication on the SPI bus
and acts on the instruction from the master.
CY14X256Q operates as a SPI slave and may share the SPI bus
with other SPI slave devices.
Chip Select (CS)
For selecting any slave device, the master needs to pull-down
the corresponding CS pin. Any instruction can be issued to a
slave device only while the CS pin is LOW. When the device is
not selected, data through the SI pin is ignored and the serial
output pin (SO) remains in a high impedance state.
Note A new instruction must begin with the falling edge of CS.
Therefore, only one opcode can be issued for each active Chip
Select cycle.
Serial Clock (SCK)
Serial clock is generated by the SPI master and the
communication is synchronized with this clock after CS goes
LOW.
CY14X256Q enables SPI modes 0 and 3 for data
communication. In both these modes, the inputs are latched by
the slave device on the rising edge of SCK and outputs are
issued on the falling edge. Therefore, the first rising edge of SCK
signifies the arrival of the first bit (MSB) of SPI instruction on the
SI pin. Further, all data inputs and outputs are synchronized with
SCK.
Data Transmission - SI/SO
SPI data bus consists of two lines, SI and SO, for serial data
communication. The SI is also referred to as Master Out Slave
In (MOSI) and SO is referred to as Master In Slave Out (MISO).
The master issues instructions to the slave through the SI pin,
while the slave responds through the SO pin. Multiple slave
devices may share the SI and SO lines as described earlier.
CY14X256Q has two separate pins for SI and SO, which can be
connected with the master as shown in Figure 4 on page 7.
Most Significant Bit (MSB)
The SPI protocol requires that the first bit to be transmitted is the
Most Significant Bit (MSB). This is valid for both address and
data transmission.
The 256-Kbit serial nvSRAM requires a 2-byte address for any
read or write operation. However, because the address is only
15-bits, it implies that the first MSB which is fed in is ignored by
the device. Although this bit is ‘don’t care’, Cypress recommends
that this bit is treated as 0 to enable seamless transition to higher
memory densities.
Serial Opcode
After the slave device is selected with CS going LOW, the first
byte received is treated as the opcode for the intended operation.
CY14X256Q uses the standard opcodes for memory accesses.
In addition to the memory accesses, it provides additional
opcodes for the nvSRAM specific functions: STORE, RECALL,
AutoStore Enable, and AutoStore Disable. See Table 2 on page
Document Number: 001-65282 Rev. *I
Page 6 of 33

6 Page



ページ 合計 : 30 ページ
 
PDF
ダウンロード
[ CY14E256Q データシート.PDF ]


データシートを活用すると、その部品の主な機能と仕様を詳しく理解できます。 ピン構成、電気的特性、動作パラメータ、性能を確認してください。


共有リンク

Link :


部品番号部品説明メーカ
CY14E256I

256-Kbit (32 K x 8) Serial (I2C) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14E256L

256-Kbit (32K x 8) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14E256LA

256-Kbit (32 K x 8) nvSRAM

Cypress Semiconductor
Cypress Semiconductor
CY14E256Q

256-Kbit (32 K x 8) SPI nvSRAM

Cypress Semiconductor
Cypress Semiconductor


www.DataSheet.jp    |   2020   |  メール    |   最新    |   Sitemap