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CY15B101N の電気的特性と機能

CY15B101NのメーカーはCypress Semiconductorです、この部品の機能は「1-Mbit (64K x 16) Automotive F-RAM Memory」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY15B101N
部品説明 1-Mbit (64K x 16) Automotive F-RAM Memory
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY15B101N Datasheet, CY15B101N PDF,ピン配置, 機能
CY15B101N
1-Mbit (64K × 16) Automotive F-RAM Memory
1-Mbit (64K × 16) Automotive F-RAM Memory
Features
1-Mbit ferroelectric random access memory (F-RAM™)
logically organized as 64K × 16
Configurable as 128K × 8 using UB and LB
High-endurance 100 trillion (1014) read/writes
151-year data retention (see the Data Retention and
Endurance table)
NoDelay™ writes
Page-mode operation for 30-ns cycle time
Advanced high-reliability ferroelectric process
SRAM compatible
Industry-standard 64K × 16 SRAM pinout
60-ns access time, 90-ns cycle time
Superior to battery-backed SRAM modules
No battery concerns
Monolithic reliability
True surface-mount solution, no rework steps
Superior for moisture, shock, and vibration
Low power consumption
Active current 7 mA (typ)
Standby current 120 A (typ)
Low-voltage operation: VDD = 2.0 V to 3.6 V
Automotive-A temperature: –40 C to +85 C
Logic Block Diagram
44-pin thin small outline package (TSOP) Type II
Restriction of hazardous substances (RoHS)-compliant
Functional Description
The CY15B101N is a 64K × 16 nonvolatile memory that reads
and writes similar to a standard SRAM. A ferroelectric random
access memory or F-RAM is nonvolatile, which means that data
is retained after power is removed. It provides data retention for
over 151 years while eliminating the reliability concerns,
functional disadvantages, and system design complexities of
battery-backed SRAM (BBSRAM). Fast write-timing and high
write-endurance make the F-RAM superior to other types of
memory.
The CY15B101N operation is similar to that of other RAM
devices, and, therefore, it can be used as a drop-in replacement
for a standard SRAM in a system. Read cycles may be triggered
by CE or simply by changing the address and write cycles may
be triggered by CE or WE. The F-RAM memory is nonvolatile
due to its unique ferroelectric memory process. These features
make the CY15B101N ideal for nonvolatile memory applications
requiring frequent or rapid writes.
The device is available in a 400-mil, 44-pin TSOP-II
surface-mount package. Device specifications are guaranteed
over the Automotive-A temperature range –40 °C to +85 °C.
For a complete list of related resources, click here.
A15-0
A15-2
A1-0
CE
WE
UB, LB
OE
ZZ
Control
Logic
64K x 16 block
F-RAM Array
...
Column Decoder
I/O Latch & Bus Driver
DQ15-0
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-96058 Rev. *D
• San Jose, CA 95134-1709 • 408-943-2600
Revised September 4, 2015

1 Page





CY15B101N pdf, ピン配列
CY15B101N
Pinout
Figure 1. 44-Pin TSOP II Pinout
A4
A3
A2
A1
A0
CE
DQ0
DQ1
DQ2
DQ3
VDD
VSS
DQ4
DQ5
DQ6
DQ7
WE
VSS
A15
A14
A13
A12
1 44
2 43
3 42
4 41
5 40
6 39
7 38
8 37
9 44-pin TSOP II 36
10 (× 16) 35
11
12 Top View
13 (not to scale)
34
33
32
14 31
15 30
16 29
17 28
18 27
19 26
20 25
21 24
22 23
A5
A6
A7
OE
UB
LB
DQ15
DQ14
DQ13
DQ12
VSS
VDD
DQ11
DQ10
DQ9
DQ8
ZZ
A8
A9
A10
A11
NC
Pin Definitions
Pin Name I/O Type
Description
A0–A15
DQ0–DQ15
WE
Input
Input/Output
Input
Address inputs: The 16 address lines select one of 64K words in the F-RAM array. The lowest two
address lines A1–A0 may be used for page mode read and write operations.
Data I/O Lines: 16-bit bidirectional data bus for accessing the F-RAM array.
Write Enable: A write cycle begins when WE is asserted. The rising edge causes the CY15B101N to
write the data on the DQ bus to the F-RAM array. The falling edge of WE latches a new column address
for page mode write cycles.
CE Input Chip Enable: The device is selected and a new memory access begins on the falling edge of CE. The
entire address is latched internally at this point. Subsequent changes to the A1–A0 address inputs allow
page mode operation.
OE Input Output Enable: When OE is LOW, the CY15B101N drives the data bus when the valid read data is
available. Deasserting OE HIGH tristates the DQ pins.
UB
Input
Upper Byte Select: Enables DQ15–DQ8 pins during reads and writes. These pins are HI-Z if UB is HIGH.
If the user does not perform byte writes and the device is not configured as a 128K × 8, the UB and LB
pins may be tied to ground.
LB
Input
Lower Byte Select: Enables DQ7–DQ0 pins during reads and writes. These pins are HI-Z if LB is HIGH.
If the user does not perform byte writes and the device is not configured as a 128 K × 8, the UB and LB
pins may be tied to ground.
ZZ Input Sleep: When ZZ is LOW, the device enters a low-power sleep mode for the lowest supply current
condition. ZZ must be HIGH for a normal read/write operation. This pin must be tied to VDD if not used.
VSS Ground Ground for the device. Must be connected to the ground of the system.
VDD Power supply Power supply input to the device.
NC No connect No connect. This pin is not connected to the die.
Document Number: 001-96058 Rev. *D
Page 3 of 19


3Pages


CY15B101N 電子部品, 半導体
CY15B101N
Maximum Ratings
Exceeding maximum ratings may shorten the useful life of the
device. These user guidelines are not tested.
Storage temperature ................................ –55 C to +125 C
Maximum accumulated storage time
At 125 °C ambient temperature ................................. 1000 h
At 85 °C ambient temperature ................................ 10 Years
Ambient temperature
with power applied ................................... –55 °C to +125 °C
Supply voltage on VDD relative to VSS ........–1.0 V to + 4.5 V
Voltage applied to outputs
in High Z state .................................... –0.5 V to VDD + 0.5 V
Input voltage .......... –1.0 V to + 4.5 V and VIN < VDD + 1.0 V
Transient voltage (< 20 ns) on
any pin to ground potential ................. –2.0 V to VCC + 2.0 V
Package power dissipation
capability (TA = 25 °C) ................................................. 1.0 W
Surface mount Pb soldering
temperature (3 seconds) ......................................... +260 C
DC output current (1 output at a time, 1s duration) .... 15 mA
Static discharge voltage
Human Body Model (AEC-Q100-002 Rev. E) ............... 2 kV
Charged Device Model (AEC-Q100-011 Rev. B) ......... 500 V
Latch-up current ................................................... > 140 mA
Operating Range
Range Ambient Temperature (TA)
VDD
Automotive-A
–40 C to +85 C
2.0 V to 3.6 V
DC Electrical Characteristics
Over the Operating Range
Parameter
VDD
IDD
Description
Power supply voltage
VDD supply current
ISB Standby current
IZZ
ILI
ILO
VIH1
VIH2
VIL1
VIL2
VOH1
VOH2
VOL1
VOL2
Sleep mode current
Input leakage current
Output leakage current
Input HIGH voltage
Input HIGH voltage
Input LOW voltage
Input LOW voltage
Output HIGH voltage
Output HIGH voltage
Output LOW voltage
Output LOW voltage
Test Conditions
VDD = 3.6 V, CE cycling at min. cycle time. All
inputs toggling at CMOS levels
(0.2 V or VDD – 0.2 V), all DQ pins unloaded.
VDD = 3.6 V, CE at VDD,
All other pins are static and at
CMOS levels
TA = 25 C
TA = 85 C
(0.2 V or VDD – 0.2 V), ZZ is HIGH
VDD = 3.6 V, ZZ is LOW,
All other inputs VSS or VDD.
TA = 25 C
TA = 85 C
VIN between VDD and VSS
VOUT between VDD and VSS
VDD = 2.7 V to 3.6 V
VDD = 2.0 V to 2.7 V
VDD = 2.7 V to 3.6 V
VDD = 2.0 V to 2.7 V
IOH = –1 mA, VDD > 2.7 V
IOH = –100 µA
IOL = 2 mA, VDD > 2.7 V
IOL = 150 µA
Min Typ [1] Max
2.0 3.3 3.6
– 7 12
– 120 150
– – 250
–35
––8
– – +1
– – +1
2.2 – VDD + 0.3
0.7 × VDD
– 0.3
0.8
– 0.3
2.4
– 0.3 × VDD
––
VDD – 0.2
0.4
– – 0.2
Unit
V
mA
µA
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
Note
1. Typical values are at 25 °C, VDD = VDD (typ). Not 100% tested.
Document Number: 001-96058 Rev. *D
Page 6 of 19

6 Page



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部品番号部品説明メーカ
CY15B101N

1-Mbit (64K x 16) Automotive F-RAM Memory

Cypress Semiconductor
Cypress Semiconductor


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