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CY14V116F7 の電気的特性と機能

CY14V116F7のメーカーはCypress Semiconductorです、この部品の機能は「16-Mbit nvSRAM」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY14V116F7
部品説明 16-Mbit nvSRAM
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY14V116F7 Datasheet, CY14V116F7 PDF,ピン配置, 機能
CY14V116F7
CY14V116G7
16-Mbit nvSRAM with Asynchronous
NAND Interface
16-Mbit nvSRAM with Asynchronous NAND Interface
Features
16-Mbit nonvolatile static random access memory (nvSRAM)
Performance up to 33 MT/s per I/O
Maximum data throughput using ×16 bus – 528 Mbps
Industry-standard asynchronous NAND Flash interface with
reduced instruction set
Shared address, data, and command bus
• Address and command bus is 8 bits
• Command is sent in one or two command cycles
• Address is sent in five address cycles
• Data bus width is ×8 or ×16 bits
Modes of operation:
Asynchronous NAND Interface I/O with 30-ns access time
Status Register with a software method for detecting the fol-
lowing:
• Nonvolatile STORE completion
• Pass/Fail condition of previous command
• Write protect status
Hands-off automatic STORE on power-down with only a small
capacitor
STORE to QuantumTrap nonvolatile elements is initiated by a
software command, a dedicated hardware pin, or AutoStore on
power-down
RECALL to SRAM initiated by software or power-up
High reliability
Infinite read, write, and RECALL cycles
1 million STORE cycles to QuantumTrap
Data retention: 20 years at 85 C
Operating voltage
Core VCC = 2.7 V to 3.6 V; I/O VCCQ = 1.70 V to 1.95 V
165-ball fine-pitch ball grid array (FBGA) package
Industrial temperature: –40 C to +85 C
Restriction of hazardous substances (RoHS) compliant
Overview
Cypress nvSRAM combines high-performance SRAM cells with
nonvolatile elements in a monolithic integrated circuit. The
embedded nonvolatile elements incorporate the
Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) technology,
producing the world's most reliable nonvolatile memory. The
SRAM can be read and written an infinite number of times. The
nonvolatile data resides in the nonvolatile elements and does not
change when data is written to the SRAM.
The CY14V116F7/CY14V116G7 nvSRAM provides access
through a standard asynchronous NAND interface and supports
the ×8 and ×16 interface options. In the case of ×16 interface,
data bytes are transmitted over the DQ[15:0] lines and has
double the throughput compared to the DQ[7:0] bus. The
CY14V116F7/ CY14V116G7 uses a highly multiplexed DQ bus
to transfer data, addresses, and instructions. All addresses and
commands are always transmitted over the data bus DQ[7:0].
Therefore, in the case of the ×16 bus interface, the upper eight
data bits DQ[15:8] become don’t care bits during the address and
command cycles. The CY14V116F7/CY14V116G7 uses five
control pins (CLE, ALE, CE, RE, and WE) to transfer command,
address, and data during read and write operations. Additional
I/O pins, such as write protect (WP), ready/busy (R/B), and HSB
STORE, are used to support features in the device.
The asynchronous NAND interface nvSRAM is aligned to a
majority of the ONFI 1.0 specifications and supports data access
speed up to 33 MHz.
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-75528 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 7, 2015

1 Page





CY14V116F7 pdf, ピン配列
CY14V116F7
CY14V116G7
Contents
Pin Configurations ........................................................... 4
Pin Definitions .................................................................. 5
Discovery and Initialization ............................................. 5
nvSRAM Bus Operations ................................................. 5
Control Signals ................................................................. 5
nvSRAM Bus Modes......................................................... 6
nvSRAM Enable/Standby............................................ 6
nvSRAM Bus Idle ........................................................ 6
nvSRAM Commands................................................... 6
nvSRAM Address Input ............................................... 7
nvSRAM Data Input..................................................... 8
nvSRAM Data Output.................................................. 8
Command Definition.................................................... 9
Basic Operations ............................................................ 10
Read ID (90h) Definition............................................ 10
Read Parameter Page (ECh) .................................... 12
Read Status (70h) Definition ..................................... 14
Status Field Definition ............................................... 15
nvSRAM Burst Mode Read (00h, 30h)...................... 15
nvSRAM Burst Write (80h, 10h) ................................ 16
Reset (FFh) Definition ............................................... 16
nvSRAM Software RECALL (FCh)............................ 17
Software STORE (84h, A5h) in nvSRAM .................. 17
nvSRAM AutoStore Disable (A3h) ............................ 17
nvSRAM AutoStore Enable (ACh)............................. 17
Write Protect.............................................................. 18
nvSRAM Store Operations............................................. 18
AutoStore Operation.................................................. 18
Hardware STORE (HSB) Operation.......................... 19
Software Store Operation.......................................... 19
nvSRAM RECALL Operations ....................................... 19
Hardware RECALL (Power Up)................................. 19
Software Recall ......................................................... 19
Maximum Ratings........................................................... 20
Operating Range............................................................. 20
DC Electrical Characteristics ........................................ 20
Data Retention and Endurance ..................................... 21
Capacitance .................................................................... 21
Thermal Resistance........................................................ 21
AC Test Conditions ........................................................ 22
AC Switching Characteristics ....................................... 23
Timing Modes............................................................ 23
nvSRAM AutoStore/Power-Up RECALL
Characteristics................................................................ 24
Hardware STORE Characteristics................................. 25
Ordering Information...................................................... 26
Ordering Code Definitions ......................................... 26
Package Diagram............................................................ 27
Acronyms ........................................................................ 28
Document Conventions ................................................. 28
Units of Measure ....................................................... 28
Document History Page ................................................. 29
Sales, Solutions, and Legal Information ...................... 31
Worldwide Sales and Design Support....................... 31
Products .................................................................... 31
PSoC® Solutions ...................................................... 31
Cypress Developer Community................................. 31
Technical Support ..................................................... 31
Document Number: 001-75528 Rev. *J
Page 3 of 31


3Pages


CY14V116F7 電子部品, 半導体
CY14V116F7
CY14V116G7
nvSRAM Bus Modes
Depending upon the input control signals status, the nvSRAM
takes any of the following bus states as defined in Table 1.
Table 1. Asynchronous NAND Interface Bus Modes
CE ALE CLE WE RE WP Bus State
1 X X X X X Standby
0 0 0 1 1 X Bus Idle
0 0 1 0 1 X Command
cycle
0 1 0 0 1 X Address cycle
0 0 0 0 1 H Write Cycle
0 0 0 1 0 X Read Cycle
0 1 1 X X X Undefined
0 0 0 0 1 L Write protect
to SRAM
Note Signal with state ‘X’ can be either > VIH or < VIL.
nvSRAM Enable/Standby
A chip enable (CE) signal is used to enable or disable the device.
When CE is driven LOW, all nvSRAM input signals are enabled.
With CE LOW, the nvSRAM can accept commands, addresses,
and data on its DQ lines. The nvSRAM is disabled when CE is
driven HIGH, even when the device is busy. The nvSRAM enters
the low-power standby mode when the device status is ready
and R/B is pulled HIGH by the external pull-up resistor. When CE
is disabled, all nvSRAM I/Os are disabled except WP, R/B, and
HSB.
nvSRAM Bus Idle
The nvSRAM goes to the bus idle state when CE, ALE, CLE are
LOW, and WE, RE are HIGH. During bus idle, all the input signals
are enabled but the commands, addresses, and data are not
latched in the device and there is also no data output from the
device.
nvSRAM Commands
A command is written from DQ[7:0] to the command register on
the rising edge of WE when CE is LOW, ALE is LOW, CLE is
HIGH, and RE is HIGH. All commands except the status register
read (70h) and reset (FFh) are ignored when the nvSRAM is
busy (RDY bit is set to ‘0’ in the status register).
Figure 3. Command Latch Cycle
CLE
CE
WE
ALE
DQ[7:0]
t CLS
t CS
t CLH
t CH
t WP
t ALS
t ALH
t DS
COMMAND
t DH
Don’t Care
Document Number: 001-75528 Rev. *J
Page 6 of 31

6 Page



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部品番号部品説明メーカ
CY14V116F7

16-Mbit nvSRAM

Cypress Semiconductor
Cypress Semiconductor


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