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PDF CYRF89235 Data sheet ( Hoja de datos )
| Número de pieza | CYRF89235 | |
| Descripción | PRoC USB | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de CYRF89235 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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CYRF89235
PRoC™ USB
PRoC™ USB
PRoC-USB Features
■ Single Device, Two Functions
❐ 8-bit, flash based USB peripheral MCU function and 2.4-GHz
radio transceiver function in a single device
■ RF Attributes
❐ Fully integrated 2.4-GHz radio on a chip
❐ 1-Mbps over-the-air data rate
❐ Transmit power typical: 0 dBm
❐ Receive sensitivity typical: –87 dBm
❐ 1 µA typical current consumption in sleep state
❐ Closed-loop frequency synthesis
❐ Supports frequency-hopping spread spectrum
❐ On-chip packet framer with 64-byte first in first out (FIFO)
data buffer
❐ Built-in auto-retry-acknowledge protocol simplifies usage
❐ Built-in cyclic redundancy check (CRC), forward error
correction (FEC), data whitening
❐ Supports DC ~ 12-MHz SPI bus interface
❐ Additional outputs for interrupt request (IRQ) generation
❐ Digital readout of received signal strength indication (RSSI)
■ MCU Attributes
❐ Powerful Harvard-architecture processor
❐ M8C processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
❐ 1.9 V to 3.6V operating voltage without USB
❐ Operating voltage with USB enabled:
• 3.15 V to 3.45 V when supply voltage is around 3.3 V
❐ Commercial temperature range: 0 °C to +70 °C
■ Flexible on-chip memory
❐ 32 KB flash program storage:
• 50,000 erase and write cycles
• Flexible protection modes
❐ Up to 2048 bytes SRAM data storage
❐ In-system serial programming (ISSP)
■ Complete development tools
❐ Free development tool PSoC Designer™
❐ Full-featured, in-circuit emulator and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128-KB trace memory
■ Precision, programmable clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator (IMO):
• 0.25% accuracy with oscillator lock to USB data, no
external components required
• Internal low-speed oscillator (ILO) at 32 kHz for watchdog
and sleep. The frequency range is 19 to 50 kHz with a
32-kHz typical value
■ Programmable pin configurations.
❐ Up to 13 general-purpose I/Os (GPIOs)
❐ 25 mA sink current on all GPIO
• 60 mA total sink current on Even port pins and 60 mA total
sink current on Odd port pins
• 120 mA total sink current on all GPIOs
❐ Pull-up, High Z, open drain, CMOS drive modes on all GPIO
❐ CMOS drive mode A –5 mA source current on ports 0 and 1
and 1 mA on port 2
• 20 mA total source current on all GPIOs
❐ Low dropout voltage regulator for Port 1 pins:
• Programmable to output 3.0, 2.5, or 1.8 V
❐ Selectable, regulated digital I/O on Port 1
❐ Configurable input threshold for Port 1
❐ Hot-swappable Capability on Port 1
■ Full-Speed USB (12 Mbps)
❐ Eight unidirectional endpoints
❐ One bidirectional control endpoint
❐ USB 2.0-compliant
❐ Dedicated 512 bytes buffer
❐ No external crystal required
■ Additional system resources
❐ Configurable communication speeds
❐ I2C slave:
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 A
• Hardware address detection
❐ SPI master and SPI slave:
• Configurable between 46.9 kHz and 12 MHz
❐ Three 16-bit timers
❐ 10-bit ADC used to monitor battery voltage or other signals
with external components
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-77748 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised May 15, 2013
1 page  
CYRF89235
Firmware is required to handle various parts of the USB
interface. The SIE issues interrupts after key USB events to
direct firmware to appropriate tasks:
■ Fill and empty the USB data buffers in USB SRAM.
■ Enable PMA channels appropriately.
■ Coordinate enumeration by decoding USB device requests.
■ Suspend and resume coordination.
■ Verify and select data toggle values.
10-bit ADC
The ADC on enCoRe V device is an independent block with a
state machine interface to control accesses to the block. The
ADC is housed together with the temperature sensor core and
can be connected to this or the Analog mux bus. As a default
operation, the ADC is connected to the temperature sensor
diodes to give digital values of the temperature.
Figure 2. ADC System Performance Block Diagram
VIN
TEMP SENSOR/ ADC
input mux or the temperature sensor with an input voltage range
of 0 V to VREFADC.
In the ADC only configuration (the ADC MUX selects the Analog
mux bus, not the default temperature sensor connection), an
external voltage can be connected to the input of the modulator
for voltage conversion. The ADC is run for a number of cycles
set by the timer, depending upon the desired resolution of the
ADC. A counter counts the number of trips by the comparator,
which is proportional to the input voltage. The Temp Sensor block
clock speed is 36 MHz and is divided down to 1 to 12 MHz for
ADC operation.
SPI
The serial peripheral interconnect (SPI) 3-wire protocol uses
both edges of the clock to enable synchronous communication
without the need for stringent setup and hold requirements.
Figure 3. Basic SPI Configuration
SPI Master
Data is output by
both the Master
and Slave on
one edge of the
clock.
SCLK
SPI Slave
Data is registered at the
input of both devices on the
opposite edge of the clock.
MOSI
MISO
TEMP
DIODES
ADC
SYSTEM BUS
INTERFACE BLOCK
COMMAND/ STATUS
Interface to the M8 C
( Processor ) Core
The ADC User Module contains an integrator block and one
comparator with positive and negative input set by the MUXes.
The input to the integrator stage comes from the analog global
A device can be a master or slave. A master outputs clock and
data to the slave device and inputs slave data. A slave device
inputs clock and data from the master device and outputs data
for input to the master. Together, the master and slave are
essentially a circular Shift register, where the master generates
the clocking and initiates data transfers.
A basic data transfer occurs when the master sends eight bits of
data, along with eight clocks. In any transfer, both master and
slave transmit and receive simultaneously. If the master only
sends data, the received data from the slave is ignored. If the
master wishes to receive data from the slave, the master must
send dummy bytes to generate the clocking for the slave to send
data back.
Figure 4. SPI Block Diagram
SPI Block
MOSI,
MOSI,
MISO DATA_IN DATA_OUT MISO
SCLK CLK_IN
CLK_OUT SCLK
SYSCLK
INT
SS_
Registers
CONFIGURATION[7:0] CONTROL[7:0]
TRANSMIT[7:0]
RECEIVE[7:0]
Document Number: 001-77748 Rev. *F
Page 5 of 45
5 Page 
CYRF89235
Pin Configuration
The PRoC-USB device is available in a 40-pin QFN package, which is illustrated in the subsequent tables.
Figure 7. 40-pin QFN pinout
Document Number: 001-77748 Rev. *F
Page 11 of 45
11 Page | ||
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| PDF Descargar | [ Datasheet CYRF89235.PDF ] | |
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