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CYRF69303 の電気的特性と機能

CYRF69303のメーカーはCypress Semiconductorです、この部品の機能は「Programmable Radio-on-Chip LPstar」です。


製品の詳細 ( Datasheet PDF )

部品番号 CYRF69303
部品説明 Programmable Radio-on-Chip LPstar
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CYRF69303 Datasheet, CYRF69303 PDF,ピン配置, 機能
CYRF69303
Programmable Radio-on-Chip LPstar
Programmable Radio-on-Chip LPstar
Features
Radio System-on-Chip with built-in 8-bit MCU in a single
device.
Operates in the unlicensed worldwide Industrial, Scientific, and
Medical (ISM) band (2.400 GHz to 2.483 GHz).
On Air compatible with second generation radio
WirelessUSB™ LP and PRoC LP.
Pin-to-pin compatible with PRoC LP except the pin 31 and
pin 37.
Intelligent
M8C based 8-bit CPU, optimized for human interface devices
(HID) applications
256 bytes of SRAM
8 Kbytes of flash memory with EEPROM emulation
In-system reprogrammable through D+/D– pins
CPU speed up to 12 MHz
16-bit free running timer
Low power wakeup timer
12-bit programmable interval timer with interrupts
Watchdog timer
Low Power
21 mA operating current (Transmit at –5 dBm)
Sleep current less than 1 A
Operating voltage from 2.7 V to 3.6 V DC
Fast startup and fast channel changes
Supports coin cell operated applications
Reliable & Robust
Receive sensitivity typical –90 dBm
AutoRate™ - Dynamic Data Rate Reception
Enables data reception for any of the supported bit rates
automatically.
DSSS (250 Kbps), GFSK (1 Mbps)
Operating temperature from 0 °C to 70 °C
Closed-loop frequency synthesis for minimal frequency drift
Simple Development
Auto transaction sequencer (ATS): MCU can remain in sleep
state longer to save power
Framing, length, CRC16, and Auto ACK
Separate 16 byte transmit and receive FIFOs
Receive signal strength indication (RSSI)
Built-in serial peripheral interface (SPI) control while in Sleep
Mode
Advanced development tools based on Cypress’s PSoC® tools
Flexible I/O
2 mA source current on all GPIO pins. Configurable 8 mA or
50 mA/pin current sink on designated pins
Each GPIO pin supports high impedance inputs, configurable
pull up, open drain output, CMOS/TTL inputs, and CMOS
output
Maskable interrupts on all I/O pins
BOM Savings
Low external component count
Small footprint 40-pin QFN (6 mm × 6 mm)
GPIOs that require no external components
Operates off a single crystal
Applications
Wireless keyboards and mice
Presentation tools
Wireless gamepads
Remote controls
Toys
Fitness
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66502 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 18, 2014

1 Page





CYRF69303 pdf, ピン配列
CYRF69303
Contents
Functional Description ..................................................... 4
Functional Overview ........................................................ 4
2.4 GHz Radio Function .............................................. 4
Data Transmission Modes ........................................... 4
Microcontroller Function .............................................. 4
Backward Compatibility ............................................... 4
Pinouts .............................................................................. 5
Pin Definitions .................................................................. 5
Functional Block Overview .............................................. 6
2.4 GHz Radio ............................................................. 6
Frequency Synthesizer ................................................ 6
Baseband and Framer ................................................. 6
Packet Buffers and Radio Configuration Registers ..... 7
Auto Transaction Sequencer (ATS) ............................ 7
Interrupts ..................................................................... 7
Clocks .......................................................................... 8
GPIO Interface ............................................................ 8
Power-on Reset ........................................................... 8
Timers ......................................................................... 8
Power Management .................................................... 8
Low Noise Amplifier (LNA) and
Received Signal Strength Indication (RSSI) ....................... 9
SPI Interface ...................................................................... 9
Three-Wire SPI Interface ............................................. 9
Four-Wire SPI Interface ............................................... 9
SPI Communication and Transactions ...................... 10
SPI I/O Voltage References ...................................... 10
SPI Connects to External Devices ............................ 10
CPU Architecture ............................................................ 11
CPU Registers ................................................................. 11
Flags Register ........................................................... 11
Accumulator Register ................................................ 12
Index Register ........................................................... 12
Stack Pointer Register ............................................... 12
CPU Program Counter High Register ....................... 12
CPU Program Counter Low Register ........................ 12
Addressing Modes ......................................................... 13
Source Immediate ..................................................... 13
Source Direct ............................................................. 13
Source Indexed ......................................................... 13
Destination Direct ...................................................... 13
Destination Indexed ................................................... 14
Destination Direct Source Immediate ........................ 14
Destination Indexed Source Immediate .................... 14
Destination Direct Source Direct ............................... 14
Source Indirect Post Increment ................................. 15
Destination Indirect Post Increment .......................... 15
Instruction Set Summary ............................................... 16
Memory Organization ..................................................... 17
Flash Program Memory Organization ....................... 17
Data Memory Organization ....................................... 18
Flash .......................................................................... 18
SROM ........................................................................ 18
SROM Function Descriptions .................................... 19
Clocking .......................................................................... 22
SROM Table Read Description ................................. 23
Clock Architecture Description .................................. 24
CPU Clock During Sleep Mode ................................. 28
Reset ................................................................................ 29
Power-on Reset ......................................................... 30
Watchdog Timer Reset .............................................. 30
Sleep Mode ...................................................................... 30
Sleep Sequence ........................................................ 30
Low Power in Sleep Mode ......................................... 31
Wakeup Sequence .................................................... 31
Power-on Reset Control ................................................. 33
POR Compare State ................................................. 33
ECO Trim Register .................................................... 33
General-Purpose I/O Ports ............................................. 34
Port Data Registers ................................................... 34
GPIO Port Configuration ........................................... 35
GPIO Configurations for Low Power Mode ............... 41
Serial Peripheral Interface (SPI) ................................ 42
SPI Data Register ...................................................... 43
SPI Configure Register .............................................. 43
SPI Interface Pins ...................................................... 45
Timer Registers .............................................................. 45
Registers ................................................................... 45
Interrupt Controller ......................................................... 48
Architectural Description ........................................... 48
Interrupt Processing .................................................. 49
Interrupt Latency ....................................................... 49
Interrupt Registers ..................................................... 49
Microcontroller Function Register Summary ............. 54
Radio Function Register Summary ............................... 56
Absolute Maximum Ratings .......................................... 57
DC Characteristics ......................................................... 57
AC Characteristics ......................................................... 59
Switching Waveforms .................................................... 60
RF Characteristics .......................................................... 63
Ordering Information ...................................................... 65
Ordering Code Definitions ......................................... 65
Package Handling ........................................................... 66
Package Diagrams .......................................................... 66
Acronyms ........................................................................ 68
Document Conventions ................................................. 68
Units of Measure ....................................................... 68
Document History Page ................................................. 69
Sales, Solutions, and Legal Information ...................... 70
Worldwide Sales and Design Support ....................... 70
Products .................................................................... 70
PSoC® Solutions ...................................................... 70
Cypress Developer Community ................................. 70
Technical Support ..................................................... 70
Document Number: 001-66502 Rev. *E
Page 3 of 70


3Pages


CYRF69303 電子部品, 半導体
CYRF69303
Pin Definitions (continued)
Pin Name
Description
27 IRQ Radio Function Interrupt output, configure High, Low or as Radio GPIO
28 P1.5 / MOSI MOSI pin from microcontroller function to radio function
29 MISO 3-wire SPI mode configured as Radio GPIO. In 4-wire SPI mode sends data to MCU function
30 XOUT Buffered CLK or Radio GPIO
31 NC Must be floating
32 P1.6 GPIO
33 VIO 2.7 V to 3.6 V to main power supply rail for Radio I/O
34
RST
Radio Reset. Connected to VCC with 0.47 F. Must have a RST=HIGH event the very first time power
is applied to the radio otherwise the state of the radio control registers is unknown
35 P1.7 GPIO
36 VDD1.8 Regulated logic bypass. Connected to 0.47 F to GND
37 GND Must be connected to ground
38 P0.7 GPIO
39
Vbat0
Connected to 2.7 V to 3.6 V main power supply, through 0.047 F bypass C
41 E-pad Must be connected to ground
42 Corner Tabs Do Not connect corner tabs
Functional Block Overview
All the blocks that make up the PRoC LPstar are presented in
this section.
2.4 GHz Radio
The radio transceiver is a dual conversion low IF architecture
optimized for power and range/robustness. The radio employs
channel matched filters to achieve high performance in the
presence of interference. An integrated Power Amplifier (PA)
provides up to 0 dBm transmit power, with an output power
control range of 30 dB in six steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 1. Internal PA Output Power Step Table
PA Setting
6
5
4
Typical Output Power (dBm)
0
–5
–10
3 –15
2 –20
1 –25
0 –30
Frequency Synthesizer
Before transmission or reception may commence, it is necessary
for the frequency synthesizer to settle. The settling time varies
depending on channel; 25 fast channels are provided with a
maximum settling time of 100 s.
The “fast channels” (<100 s settling time) are every third
frequency, starting at 2400 MHz up to and including 2472 MHz
(that is, 0,3,6,9…….69 and 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception and CRC16
generation and checking, and EOP detection and length field.
Data Transmission Modes and Data Rates
The SoC supports two different data transmission modes:
In GFSK mode, data is transmitted at 1 Mbps, without any
DSSS.
In DSSS mode eight bits (8DR, 32 chip) are encoded in each
derived code symbol transmitted, resulting in effective 250 kbps
data rate.
32 chip Pseudo Noise (PN) codes are supported. The two data
transmission modes apply to the data after the SOP. In particular
the length, data, and CRC16 are all sent in the same mode. In
general, DSSS reduce packet error rate in any environment.
Link Layer Modes
SOP
Packets begin with a two-symbol SoP marker. If framing is
disabled then an SOP event is inferred whenever two successive
correlations are detected. The SOP_CODE_ADR code used for
the SOP is different from that used for the “body” of the packet,
and if desired may be a different length. SOP must be configured
to be the same length on both sides of the link.
Length
Length field is the first eight bits after the SOP symbol, and is
transmitted at the payload data rate. An EoP condition is inferred
after reception of the number of bytes defined in the length field,
plus two bytes for the CRC16.
Document Number: 001-66502 Rev. *E
Page 6 of 70

6 Page



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部品番号部品説明メーカ
CYRF69303

Programmable Radio-on-Chip LPstar

Cypress Semiconductor
Cypress Semiconductor


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