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PDF CY7C60445 Data sheet ( Hoja de datos )
| Número de pieza | CY7C60445 | |
| Descripción | Low Voltage Microcontroller | |
| Fabricantes | Cypress Semiconductor | |
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CY7C604XX
enCoRe™ V Low Voltage Microcontroller
Features
■ Powerful Harvard Architecture processor
❐ M8C processor speeds running up to 24 MHz
❐ Low power at high processing speeds
❐ Interrupt controller
❐ 1.71 V to 3.6 V operating voltage
❐ Commercial temperature range: 0 °C to +70 °C
■ Flexible on-chip memory
❐ Up to 32 K flash program storage
• 50,000 erase and write cycles
• Flexible protection modes
❐ Up to 2048 bytes SRAM data storage
❐ In-system serial programming (ISSP)
■ Complete development tools
❐ Free development tool (PSoC® Designer™)
❐ Full-featured, in-circuit emulator and programmer
❐ Full-speed emulation
❐ Complex breakpoint structure
❐ 128 K trace memory
■ Precision, programmable clocking
❐ Crystal-less oscillator with support for an external crystal or
resonator
❐ Internal ±5.0% 6, 12, or 24 MHz main oscillator
❐ Internal low-speed oscillator at 32 kHz for watchdog and
sleep. The frequency range is 19 to 50 kHz with a 32 kHz
typical value
enCoRe V LV Block Diagram
enCoRe V
CORE
SRAM
2048 Bytes
Interrupt
Controller
■ Programmable pin configurations
❐ Up to 36 GPIO (depending on package)
❐ 25 mA sink current on all GPIO
❐ Pull-up, High Z, open drain, CMOS drive modes on all GPIO
❐ CMOS drive mode (5 mA source current) on Ports 0 and 1:
• 20 mA (at 3.0 V) total source current
❐ Low dropout voltage regulator for Port 1 pins:
• Programmable to output 3.0, 2.5, or 1.8V
❐ Selectable, regulated digital I/O on Port 1
❐ Configurable input threshold for Port 1
❐ Hot-swappable capability on Port 1
■ Additional system resources
❐ Configurable communication speeds
❐ I2C Slave
• Selectable to 50 kHz, 100 kHz, or 400 kHz
• Implementation requires no clock stretching
• Implementation during sleep modes with less than 100 mA
• Hardware address detection
❐ SPI master and SPI slave
• Configurable between 46.9 kHz and 12 MHz
❐ Three 16-bit timers
❐ 10-bit ADC used to monitor battery voltage or other signals
with external components
❐ Watchdog and sleep timers
❐ Integrated supervisory circuit
Port 4 Port 3 Port 2 Port 1 Port 0 Prog. LDO
SROM
8 K / 16 K / 32 K
Flash
CPU Core (M8C)
System Bus
Sleep and
Watchdog
6 / 12 / 24 MHz Internal Main Oscillator
ADC
3 16-Bit
Timers
I2C Slave/SPI
Master-Slave
POR and LVD
System Resets
System Resources
Errata: For information on silicon errata, see “Errata” on page 33. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-12395 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised November 12, 2013
1 page  
CY7C604XX
The basic I2C features include:
■ ✟Slave, transmitter, and receiver operation
■ ✟Byte processing for low CPU overhead
■ ✟Interrupt or polling CPU interface
■ ✟Support for clock rates of up to 400 kHz
■ ✟7- or 10-bit addressing (through firmware support)
■ ✟SMBus operation (through firmware support)
Enhanced features of the I2C Slave Enhanced Module include:
■ ✟Support for 7-bit hardware address compare
■ ✟Flexible data buffering schemes
■ ✟A ‘no bus stalling’ operating mode
■ ✟A low power bus monitoring mode
The I2C block controls the data (SDA) and the clock (SCL) to the
external I2C interface through direct connections to two
dedicated GPIO pins. When I2C is enabled, these GPIO pins are
not available for general purpose use. The enCoRe V LV CPU
firmware interacts with the block through I/O register reads and
writes, and firmware synchronization is implemented through
polling and/or interrupts.
In the default operating mode, which is firmware compatible with
previous versions of I2C slave modules, the I2C bus is stalled
upon every received address or byte, and the CPU is required to
read the data or supply data as required before the I2C bus
continues. However, this I2C Slave Enhanced module provides
new data buffering capability as an enhanced feature. In the
EZI2C buffering mode, the I2C slave interface appears as a
32-byte RAM buffer to the external I2C master. Using a simple
predefined protocol, the master controls the read and write
pointers into the RAM. When this method is enabled, the slave
never stalls the bus. In this protocol, the data available in the
RAM (this is managed by the CPU) is valid.
Additional System Resources
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include low voltage detection and power on
reset. The following statements describe the merits of each
system resource:
■ Low-voltage detection (LVD) interrupts can signal the appli-
cation of falling voltage levels, while the advanced power-on
reset (POR) circuit eliminates the need for a system supervisor.
■ The 3.6 V maximum input, 1.8, 2.5, or 3 V selectable output,
low dropout regulator (LDO) provides regulation for I/Os. A
register controlled bypass mode enables the user to disable
the LDO.
■ Standard Cypress PSoC IDE tools are available for debugging
the enCoRe V LV family of parts.
Getting Started
The quickest way to understanding the enCoRe V silicon is by
reading this datasheet and using the PSoC Designer Integrated
Development Environment (IDE). This datasheet is an overview
of the enCoRe V integrated circuit and presents specific pin,
register, and electrical specifications. For in-depth information,
along with detailed programming information, refer to the PSoC
Programmable System-on-Chip Technical Reference Manual,
for CY8C28xxx PSoC devices.
For up-to-date ordering, packaging, and electrical specification
information, reference the latest enCoRe V device datasheets on
the web at http://www.cypress.com.
Application Notes
Cypress application notes are an excellent introduction to the
wide variety of possible PSoC designs.
Development Kits
PSoC Development Kits are available online from and through a
growing number of regional and global distributors, which
include Arrow, Avnet, Digi-Key, Farnell, Future Electronics, and
Newark.
Training
Free PSoC technical training (on demand, webinars, and
workshops), which is available online via www.cypress.com,
covers a wide variety of topics and skill levels to assist you in
your designs.
CYPros Consultants
Certified PSoC consultants offer everything from technical assis-
tance to completed PSoC designs. To contact or become a PSoC
consultant go to the CYPros Consultants web site.
Solutions Library
Visit our growing library of solution focused designs. Here you
can find various application designs that include firmware and
hardware design files that enable you to complete your designs
quickly.
Technical Support
Technical support – including a searchable Knowledge Base
articles and technical forums – is also available online. If you
cannot find an answer to your question, call our Technical
Support hotline at 1-800-541-4736.
Document Number: 001-12395 Rev. *P
Page 5 of 37
5 Page 
48-Pin Part Pinout
Figure 7. CY7C60455/CY7C60456 48-Pin enCoRe V LV Device
CY7C604XX
NC
P2[7]
P2[5]
P2[3]
P2[1]
P4[3]
P4[1]
P3[7]
P3[5]
P3[3]
P3[1]
P1[7]
1
2
3
4
5
6
7
8
9
10
11
12
QFN
(Top View)
36 P2[6]
35 P2[4]
34 P2[2]
33 P2[0]
32 P4[2]
31 P4[0]
30 P3[6]
29 P3[4]
28 P3[2]
27 P3[0]
26 XRES
25 P1[6]
Table 3. 48-Pin Part Pinout (QFN)
Pin No.
Type
Name
1 NC NC
2 I/O P2[7]
3 I/O P2[5]
4 I/O P2[3]
5 I/O P2[1]
6 I/O P4[3]
7 I/O P4[1]
8 I/O P3[7]
9 I/O P3[5]
10 I/O P3[3]
11 I/O P3[1]
12
IOHR
P1[7]
13
IOHR
P1[5]
14 NC NC
15 NC NC
16
IOHR
P1[3]
17
IOHR
P1[1](1,2)
18
Power
Vss
19 NC NC
20 NC NC
21
Power
Vdd
Description
No connection
Digital I/O
Digital I/O, crystal out (Xout)
Digital I/O, crystal in (Xin)
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O
Digital I/O, I2C SCL, SPI SS
Digital I/O, I2C SDA, SPI MISO
No connection
No connection
Digital I/O, SPI CLK
Digital I/O, ISSP CLK, I2C SCL, SPI MOSI
Supply ground
No connection
No connection
Supply voltage
Document Number: 001-12395 Rev. *P
Page 11 of 37
11 Page | ||
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| PDF Descargar | [ Datasheet CY7C60445.PDF ] | |
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