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PDF CY7C60323 Data sheet ( Hoja de datos )
| Número de pieza | CY7C60323 | |
| Descripción | enCoRe III Low Voltage | |
| Fabricantes | Cypress Semiconductor | |
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CY7C603xx
enCoRe™ III Low Voltage
enCoRe™ III Low Voltage
Features
■ Powerful Harvard-architecture processor
❐ M8C processor speeds to 12 MHz
❐ Low power at high speed
❐ 2.4 V to 3.6 V operating voltage
❐ Operating voltages down to 1.0 V using on-chip switch mode
pump (SMP)
❐ Commercial temperature range: 0 °C to +70 °C
■ Configurable peripherals
❐ 8-bit timers, counters, and PWM
❐ Full duplex master or slave SPI
❐ 10-bit ADC
❐ 8-bit successive approximation ADC
❐ Comparator
■ Flexible on-chip memory
❐ 8K flash program storage 50,000 erase/write cycles
❐ 512 bytes SRAM data storage
❐ In-System serial programming (ISSP)
❐ Partial flash updates
❐ Flexible protection modes
❐ EEPROM emulation in flash
■ Complete development tools
❐ Free development software (PSoC® Designer™)
❐ Full-featured, In-circuit emulator and programmer
❐ Complex breakpoint structure
❐ 128K trace memory
■ Precision, programmable clocking
❐ Internal ±2.5% 24 and 48 MHz oscillator
❐ Internal oscillator for watchdog and sleep
■ Programmable pin configurations
❐ 10 mA drive on all general purpose I/O (GPIO)
❐ Pull-up, pull-down, high-Z, strong, or open drain drive modes
on all GPIO
❐ Up to 8 analog inputs on GPIO
❐ Configurable interrupt on all GPIO
■ Versatile analog mux
❐ Common internal analog bus
❐ Simultaneous connection of IO combinations
■ Additional system resources
❐ I2C master, slave, and Multimaster to 400 kHz
❐ Watchdog and sleep timers
❐ User-configurable low-voltage detection
❐ Integrated supervisory circuit
❐ On-chip precision voltage reference
Applications
■ Wireless mice
■ Wireless gamepads
■ Wireless presenter tools
■ Wireless keypads
■ PlayStation® 2 wired gamepads
■ PlayStation 2 bridges for wireless gamepads
❐ Applications requiring a cost effective low voltage 8-bit
microcontroller.
Logic Block Diagram
Port 3 Port 2 Port 1 Port 0
System Bus
Global Digital
Interconnect
SRAM
512 Bytes
Interrupt
Controller
Global Analog Interconnect
SROM Flash 8K
CPU Core
(M8C)
Sleep and
Watchdog
Clock Sources (Includes IMO and ILO)
enCoRe III LV Core
DIGITAL
SYSTEM
Digital
PSoC
Block
Array
ANALOG SYSTEM
Analog
PSoC
Block
Array
Analog
Ref.
Digital
Clocks
POR and LVD Switch Internal
I2C Mode Voltage
System Resets Pump
Ref.
SYSTEM RESOURCES
Analog
Mux
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-16018 Rev. *P
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 14, 2015
1 page  
CY7C603xx
Development Tools
PSoC Designer™ is the revolutionary integrated design
environment (IDE) that you can use to customize PSoC to meet
your specific application requirements. PSoC Designer software
accelerates system design and time to market. Develop your
applications using a library of precharacterized analog and digital
peripherals (called user modules) in a drag-and-drop design
environment. Then, customize your design by leveraging the
dynamically generated application programming interface (API)
libraries of code. Finally, debug and test your designs with the
integrated debug environment, including in-circuit emulation and
standard software debug features. PSoC Designer includes:
■ Application editor graphical user interface (GUI) for device and
user module configuration and dynamic reconfiguration
■ Extensive user module catalog
■ Integrated source-code editor (C and assembly)
■ Free C compiler with no size restrictions or time limits
■ Built-in debugger
■ In-circuit emulation
■ Built-in support for communication interfaces:
❐ Hardware and software I2C slaves and masters
❐ Full-speed USB 2.0
❐ Up to four full-duplex universal asynchronous
receiver/transmitters (UARTs), SPI master and slave, and
wireless
PSoC Designer supports the entire library of PSoC 1 devices and
runs on Windows XP, Windows Vista, and Windows 7.
PSoC Designer Software Subsystems
Design Entry
In the chip-level view, choose a base device to work with. Then
select different onboard analog and digital components that use
the PSoC blocks, which are called user modules. Examples of
user modules are analog-to-digital converters (ADCs),
digital-to-analog converters (DACs), amplifiers, and filters.
Configure the user modules for your chosen application and
connect them to each other and to the proper pins. Then
generate your project. This prepopulates your project with APIs
and libraries that you can use to program your application.
The tool also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
reconfiguration makes it possible to change configurations at run
time. In essence, this lets you to use more than 100 percent of
PSoC's resources for an application.
Code Generation Tools
The code generation tools work seamlessly within the
PSoC Designer interface and have been tested with a full range
of debugging tools. You can develop your design in C, assembly,
or a combination of the two.
Assemblers. The assemblers allow you to merge assembly
code seamlessly with C code. Link libraries automatically use
absolute addressing or are compiled in relative mode, and linked
with other software modules to get absolute addressing.
C Language Compilers. C language compilers are available
that support the PSoC family of devices. The products allow you
to create complete C programs for the PSoC family devices. The
optimizing C compilers provide all of the features of C, tailored
to the PSoC architecture. They come complete with embedded
libraries providing port and bus operations, standard keypad and
display support, and extended math functionality.
Debugger
PSoC Designer has a debug environment that provides
hardware in-circuit emulation, allowing you to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow you to read and program and
read and write data memory, and read and write I/O registers.
You can read and write CPU registers, set and clear breakpoints,
and provide program run, halt, and step control. The debugger
also lets you to create a trace buffer of registers and memory
locations of interest.
Online Help System
The online help system displays online, context-sensitive help.
Designed for procedural and quick reference, each functional
subsystem has its own context-sensitive help. This system also
provides tutorials and links to FAQs and an Online Support
Forum to aid the designer.
In-Circuit Emulator
A low-cost, high-functionality in-circuit emulator (ICE) is
available for development support. This hardware can program
single devices.
The emulator consists of a base unit that connects to the PC
using a USB port. The base unit is universal and operates with
all PSoC devices. Emulation pods for each device family are
available separately. The emulation pod takes the place of the
PSoC device in the target board and performs full-speed
(24 MHz) operation.
Document Number: 38-16018 Rev. *P
Page 5 of 40
5 Page 
CY7C603xx
Register Reference
This section lists the registers of the enCoRe III LV device. For
detailed register information, refer the PSoC System-on-Chip
Technical Reference Manual.
Register Conventions
The register conventions specific to this section are listed in
Table 4.
Table 4. Register Conventions
Convention
Description
R Read register or bit(s)
W Write register or bit(s)
L Logical register or bit(s)
C Clearable register or bit(s)
# Access is bit specific
Register Mapping Tables
The enCoRe III LV device has a total register address space of
512 bytes. The register space is referred to as IO space and is
divided into two banks, Bank 0 and Bank 1. The XOI bit in the
Flag register (CPU_F) determines which bank the user is
currently in. When the XOI bit is set to 1 the user is in Bank 1.
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Table 5. Register Map 0 Table: User Space
Name
Addr
(0,Hex) Access
Name
Addr
(0,Hex)
PRT0DR
00 RW
40
PRT0IE
01 RW
41
PRT0GS
02 RW
42
PRT0DM2
03 RW
43
PRT1DR
04 RW
44
PRT1IE
05 RW
45
PRT1GS
06 RW
46
PRT1DM2
07 RW
47
PRT2DR
08 RW
48
PRT2IE
09 RW
49
PRT2GS
0A RW
4A
PRT2DM2
0B RW
4B
PRT3DR
0C RW
4C
PRT3IE
0D RW
4D
PRT3GS
0E RW
4E
PRT3DM2
0F RW
4F
10 50
11 51
12 52
13 53
14 54
15 55
16 56
17 57
18 58
19 59
1A 5A
1B 5B
1C 5C
Blank fields are Reserved and must not be accessed.
Access
Name
Addr
(0,Hex)
ASE10CR0
80
81
82
83
ASE11CR0
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
# Access is bit specific.
Access
RW
Name
RW
CUR_PP
STK_PP
IDX_PP
MVR_PP
MVW_PP
I2C_CFG
I2C_SCR
I2C_DR
I2C_MSCR
INT_CLR0
INT_CLR1
Addr
(0,Hex)
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
Access
RW
RW
RW
RW
RW
RW
#
RW
#
RW
RW
Document Number: 38-16018 Rev. *P
Page 11 of 40
11 Page | ||
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