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CYRF6986 の電気的特性と機能

CYRF6986のメーカーはCypress Semiconductorです、この部品の機能は「LPstar 2.4 GHz Radio SoC」です。


製品の詳細 ( Datasheet PDF )

部品番号 CYRF6986
部品説明 LPstar 2.4 GHz Radio SoC
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CYRF6986 Datasheet, CYRF6986 PDF,ピン配置, 機能
CYRF6986
WirelessUSB™ LPstar 2.4 GHz
Radio SoC
WirelessUSB™ LPstar 2.4 GHz Radio SoC
Features
2.4 GHz direct sequence spread spectrum (DSSS) radio trans-
ceiver
Operates in the unlicensed worldwide Industrial, Scientific, and
Medical (ISM) band (2.400 GHz to 2.483 GHz)
On Air compatible with second generation radio
WirelessUSB™ LP and PRoC LP
Pin-to-pin compatible with WirelessUSB LP except the Pin30
and Pin37
Low Power
Operating current: 21 mA (transmit at –5 dBm)
Sleep current less than 1 A
Operating voltage: 2.7 V to 3.6 V
Fast startup and fast channel changes
Supports coin-cell operated applications
Reliable and Robust
Receive Sensitivity typical –90 dBm
AutoRate™ – dynamic data rate reception
Enables data reception for any of the supported bit rates
automatically.
DSSS (250 Kbps), GFSK (1 Mbps)
Operating Temperature: 0 °C to 70 °C
Closed-loop frequency synthesis for minimal frequency drift
Logic Block Diagram
Simple Development
Auto transaction sequencer (ATS): Enables MCU to sleep
longer
Framing, length, CRC16, and auto ACK
Separate 16-byte transmit and receive FIFOs
Receive signal strength indication (RSSI)
Serial peripheral interface (SPI) control while in sleep mode
4 MHz SPI microcontroller interface
BOM Savings
Low external component count
Battery voltage monitoring circuitry
Small footprint 40-pin QFN (6 mm × 6 mm)
Applications
Wireless keyboards and mice
Presentation tools
Wireless gamepads
Remote controls
Toys
Fitness
Applications Support
See www.cypress.com for development tools, reference
designs, and application notes.
IRQ
SS
SCK
MISO
MOSI
RST
Data
Interface
and
Sequencer
DSSS
Baseband
& Framer
SPI
RSSI
Power Management
VBAT
VDD
GFSK
Modulator
Frequency
Synthesizer
GFSK
Demodulator
VCC GND
RFP
RFN
RFBIAS
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-66073 Rev. *E
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 31, 2017

1 Page





CYRF6986 pdf, ピン配列
CYRF6986
Functional Description
The CYRF6986 WirelessUSB LPstar radio is a second generation member of the Cypress WirelessUSB Radio System-On-Chip (SoC)
family. The CYRF6986 IC adds a range of enhanced features, including reduced supply current in all operating modes, reduced crystal
start up, synthesizer settling, and link turnaround times.
Pinouts
Figure 1. 40-pin QFN pinout
XTAL 1
NC 2
VCC 3
NC 4
NC 5
VBAT1 6
VCC 7
VBAT2 8
NC 9
RFBIAS 10
CYRF6986
WirelessUSB LPstar
40-Pin QFN
* E-PAD Bottom Side
30 NC
29 XOUT / GPIO
28 MISO / GPIO
27 MOSI / SDAT
26 IRQ / GPIO
25 SCK
24 SS
23 NC
22 NC
21 NC
Pin Definitions
Pin Number
1
2, 4, 5, 9, 14,
15, 17, 18, 20,
21, 22, 23, 31,
32, 36, 39
3, 7, 16, 40
6, 8, 38
10
11
12
13
19
24
25
26
27
Name
XTAL
NC
VCC
VBAT(0-2)
RFBIAS
RFP
GND
RFN
RESV
SS
SCK
IRQ
MOSI
Type
I
NC
Pwr
Pwr
O
I/O
GND
IO
I
I
I
I/O
I/O
Default
I
12 MHz crystal.
Connect to GND.
Description
VCC = 2.7 V to 3.6 V.
VBAT = 2.7 V to 3.6 V. Main supply.
O RF IO 1.8 V reference voltage.
I Differential RF signal to and from antenna.
Ground.
I Differential RF signal to and from antenna.
Must be connected to GND.
I SPI enable, active LOW assertion. Enables and frames transfers.
I SPI clock.
O Interrupt output (configurable active HIGH or LOW), or GPIO.
I SPI data input pin (Master Out Slave In), or SDAT.
Document Number: 001-66073 Rev. *E
Page 3 of 23


3Pages


CYRF6986 電子部品, 半導体
CYRF6986
control range of 35 dB in six steps. The supply current of the
device is reduced as the RF output power is reduced.
Table 1. Internal PA Output Power Step Table
PA Setting
Typical Output Power (dBm)
60
5 –5
4 –13
3 –18
2 –24
1 –30
0 –35
Frequency Synthesizer
Before transmission or reception may begin, the frequency
synthesizer must settle. The settling time varies depending on
channel; 25 fast channels are provided with a maximum settling
time of 100 s.
The ‘fast channels’ (less than 100 s settling time) are every third
channel, starting at 0 up to and including 72 (for example, 0, 3,
6, 9 …. 69, 72).
Baseband and Framer
The baseband and framer blocks provide the DSSS encoding
and decoding, SOP generation and reception, CRC16
generation and checking, and EOP detection and length field.
Packet Buffers and Radio Configuration Registers
Packet data and configuration registers are accessed through
the SPI interface. All configuration registers are directly
addressed through the address field in the SPI packet.
Configuration registers allow configuration of DSSS PN codes,
data rate, operating mode, interrupt masks, interrupt status, and
so on.
SPI Interface
The CYRF6986 IC has an SPI interface supporting
communication between an application MCU and one or more
slave devices (including the CYRF6986). The SPI interface
supports single-byte and multi-byte serial transfers using either
4-pin or 3-pin interfacing. The SPI communications interface
consists of Slave Select (SS), Serial Clock (SCK), Master
Out-Slave In (MOSI), Master In-Slave Out (MISO), or Serial Data
(SDAT).
SPI communication may be described as the following:
Command Direction (bit 7) = ‘1’ enables SPI write transaction.
A ‘0’ enables SPI read transactions.
Command Increment (bit 6) = ‘1’ enables SPI auto address
increment. When set, the address field automatically increments
at the end of each data byte in a burst access. Otherwise the
same address is accessed.
Six bits of address
Eight bits of data
The device receives SCK from an application MCU on the SCK
pin. Data from the application MCU is shifted in on the MOSI pin.
Data to the application MCU is shifted out on the MISO pin. The
active LOW Slave Select (SS) pin must be asserted to initiate an
SPI transfer.
The application MCU can initiate SPI data transfers using a
multi-byte transaction. The first byte is the Command/Address
byte, and the following bytes are the data bytes shown in Table 2
through Figure 6 on page 7.
The SPI communications interface has a burst mechanism,
where the first byte can be followed by as many data bytes as
required. A burst transaction is terminated by deasserting the
slave select (SS = 1).
The SPI communications interface single read and burst read
sequences are shown in Figure 4 on page 7 and Figure 5 on
page 7, respectively.
The SPI communications interface single write and burst write
sequences are shown in Figure 6 on page 7 and Figure 7 on
page 7, respectively.
This interface may be optionally operated in a 3-pin mode with
the MISO and MOSI functions combined in a single bidirectional
data pin (SDAT). When using 3-pin mode, user firmware must
ensure that the MOSI pin on the MCU is in a high impedance
state except when MOSI is actively transmitting data.
The device registers may be written to or read from one byte at
a time, or several sequential register locations may be written or
read in a single SPI transaction using incrementing burst mode.
In addition to single byte configuration registers, the device
includes register files. Register files are FIFOs written to and
read from using nonincrementing burst SPI transactions.
The IRQ pin function may be optionally multiplexed onto the
MOSI pin. When this option is enabled, the IRQ function is not
available while the SS pin is LOW. When using this configuration,
user firmware must ensure that the MOSI pin on the MCU is in a
high impedance state whenever the SS pin is HIGH.
The SPI interface is not dependent on the internal 12 MHz clock.
Registers may therefore be read from or written to when the
device is in sleep mode, and the 12 MHz oscillator disabled.
The SPI interface and the IRQ and RST pins have a separate
voltage reference pin (VIO). This enables the device to interface
directly to MCUs operating at voltages below the CYRF6986 IC
supply voltage.
Table 2. SPI Transaction Format
Parameter
Bit #
Bit Name
7
DIR
6
INC
Byte 1
[5:0]
Address
Byte 1+N
[7:0]
Data
Document Number: 001-66073 Rev. *E
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6 Page



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部品番号部品説明メーカ
CYRF6986

LPstar 2.4 GHz Radio SoC

Cypress Semiconductor
Cypress Semiconductor


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