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CYPD3125 の電気的特性と機能

CYPD3125のメーカーはCypress Semiconductorです、この部品の機能は「USB Type-C Port Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 CYPD3125
部品説明 USB Type-C Port Controller
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CYPD3125 Datasheet, CYPD3125 PDF,ピン配置, 機能
EZ-PD™ CCG3
USB Type-C Port Controller
General Description
EZ-PD™ CCG3 is a highly integrated USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD
CCG3 provides a complete USB Type-C and USB-Power Delivery port control solution for notebooks, dongles, monitors, docking
stations and power adapters. CCG3 uses Cypress’s proprietary M0S8 technology with a 32-bit, 48-MHz ARM® Cortex® -M0 processor
with 128-KB flash, 8-KB SRAM, 20 GPIOs, full-speed USB device controller, a Crypto engine for authentication, a 20V-tolerant
regulator, and a pair of FETs to switch a 5V (VCONN) supply, which powers cables. CCG3 also integrates two pairs of gate drivers to
control external VBUS FETs and system level ESD protection. CCG3 is available in 40-QFN, 32-QFN, and 42-WLCSP packages.
Features
Type-C and USB-PD Support
Integrated USB Power Delivery 3.0 support
Integrated USB-PD BMC transceiver
Integrated VCONN FETs
Configurable resistors RA, RP and RD
Dead Battery Detection support
Integrated fast role swap and extended data messaging
Supports one USB Type-C port
Integrated Hardware based overcurrent protection (OCP) and
overvoltage protection (OVP)
32-bit MCU Subsystem
48-MHz ARM Cortex-M0 CPU
128-KB Flash
8-KB SRAM
Integrated Digital Blocks
Hardware Crypto block enables Authentication
Full-Speed USB Device Controller supporting Billboard Device
Class
Integrated timers and counters to meet response times
required by the USB-PD protocol
Four run-time reconfigurable serial communication blocks
(SCBs) with reconfigurable I2C, SPI, or UART functionality
Clocks and Oscillators
Integrated oscillator eliminating the need for external clock
Power
2.7 V to 21.5 V operation
2x Integrated dual-output gate drivers for external VBUS FET
switch control
Independent supply voltage pin for GPIO that allows 1.71 V to
5.5 V signaling on the I/Os
Reset: 30 µA, Deep Sleep: 30 µA, Sleep: 3.5 mA
System-Level ESD Protection
On CC, SBU, DPLUS, DMINUS and VBUS pins
± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
Packages
40-pin QFN, 32-pin QFN, and 42-ball CSP for
Notebooks/Accessories
Supports industrial temperature range (–40 °C to +105 °C)
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 002-03288 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 13, 2017

1 Page





CYPD3125 pdf, ピン配列
EZ-PD™ CCG3
Contents
EZ-PD CCG3 Block Diagram ............................................ 4
Functional Overview ........................................................ 5
CPU and Memory Subsystem ..................................... 5
Crypto Block ................................................................ 5
Integrated Billboard Device ......................................... 5
USB-PD Subsystem (USBPD SS) .............................. 5
Full-Speed USB Subsystem ........................................ 6
Peripherals .................................................................. 6
GPIO ........................................................................... 7
Power Systems Overview ................................................ 8
Pinouts .............................................................................. 9
Available Firmware and Software Tools ....................... 13
EZ-PD Configuration Utility ....................................... 13
CCG3 Programming and Bootloading .......................... 14
Programming the Device Flash over SWD
Interface ..................................................................... 14
Application Firmware Update over Specific
Interfaces (I2C, CC, USB) ......................................... 14
Applications .................................................................... 17
Electrical Specifications ................................................ 23
Absolute Maximum Ratings ....................................... 23
Device-Level Specifications ...................................... 24
Digital Peripherals ..................................................... 26
System Resources .................................................... 28
Ordering Information ...................................................... 34
Ordering Code Definitions ......................................... 34
Packaging ........................................................................ 35
Acronyms ........................................................................ 38
Document Conventions ................................................. 39
Units of Measure ....................................................... 39
References and Links to Applications Collaterals ..... 40
Document History Page ................................................. 41
Sales, Solutions, and Legal Information ...................... 45
Worldwide Sales and Design Support ....................... 45
Products .................................................................... 45
PSoC® Solutions ...................................................... 45
Cypress Developer Community ................................. 45
Technical Support ..................................................... 45
Document Number: 002-03288 Rev. *H
Page 3 of 45


3Pages


CYPD3125 電子部品, 半導体
EZ-PD™ CCG3
The OV/UV (Over-Voltage/Under-Voltage) block monitors the
VBUS_C supply for programmable over-voltage and
under-voltage conditions. The CSA amplifies the voltage across
an external sense resistor, which is proportional to the current
being drawn from the external DC-DC VBUS supply converter.
The CSA output can either be measured with an ADC or
configured to detect an over-current condition. The VBUS_P and
VBUS_C gate drivers control the gates of external power FETs
for the VBUS_C and VBUS_P supplies. The gate drivers can be
configured to support both P and N type external power FETs.
The gate drivers are configured by default for nFET devices. In
applications using pFETs, the gate drivers must be appropriately
configured. The OV/UV and CSA blocks can generate interrupts
to automatically turn off the power FETs for the programmed
over-voltage and over-current conditions. The VBUS_C
discharge switch allows for discharging the VBUS_C line
through an external resistor.
The USB-PD sub-system also contains two 8-bit Successive
Approximation Register (SAR) ADCs for analog to digital
conversions. Each ADC includes an 8-bit DAC and a
comparator. The DAC output forms the positive input of the
comparator. The negative input of the comparator is from a
4-input multiplexer. The four inputs of the multiplexer are a pair
of global analog multiplex busses, an internal bandgap voltage
and an internal voltage proportional to the absolute temperature.
Each GPIO pin can be connected to the global Analog Multiplex
Busses through a switch, which allows either ADC to sample the
pin voltage. When sensing the GPIO pin voltage with an ADC,
the pin voltage cannot exceed the VDDD or VDDIO supply
values.
Figure 2. USB-PD Subsystem
charger
dc-dc
CONSUMER N/PFETs
PRODUCER N/PFETs
VBUS_P
OC VBUS_P_CTRL
CSA
Gate
Driver
VDDD
VSYS
VCONN
V5V
RA
Leaker
POWER
SWITCH
VCONN
SWITCH
AUX_P
AUX_N
PROGRAMMABLE
PULL-UP, PULL-DOWN
HPD
HPD
2x
ADCs
USB 2.0
FS PHY
VBUS_C_CTRL
Gate
Driver
LDO
OV/UV
BMC
PHY w/ FRS
ANALOG
CROSS-BAR
CHARGER
DETECT
VBUS_DISCHARGE
VBUS_C
CC1
CC2
SBU1
SBU2
DP
DM
USB PD SubSystem
Full-Speed USB Subsystem
The FSUSB subsystem contains a full speed USB device
controller as described in the Integrated Billboard Device
section.
Peripherals
Serial Communication Blocks (SCB)
EZ-PD CCG3 has four SCBs, which can be configured to
implement an I2C, SPI, or UART interface. The hardware I2C
blocks implement full multi-master and slave interfaces capable
of multimaster arbitration. In the SPI mode, the SCB blocks can
be configured to act as master or slave.
In the I2C mode, the SCB blocks are capable of operating at
speeds of up to 1 Mbps (Fast Mode Plus) and have flexible
buffering options to reduce interrupt overhead and latency for the
CPU. These blocks also support I2C that creates a mailbox
address range in the memory of EZ-PD CCG3 and effectively
reduce I2C communication to reading from and writing to an
array in memory. In addition, the blocks support 8-deep FIFOs
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204).
The I2C bus I/Os are implemented with GPIO in open-drain
modes.
Document Number: 002-03288 Rev. *H
Page 6 of 45

6 Page



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共有リンク

Link :


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