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Número de pieza | CYPD1104-35FNXIT | |
Descripción | USB Type-C Port Controller | |
Fabricantes | Cypress Semiconductor | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de CYPD1104-35FNXIT (archivo pdf) en la parte inferior de esta página. Total 19 Páginas | ||
No Preview Available ! CYPD1104-35FNXIT Datasheet
USB Type-C Port Controller with
Power Delivery
General Description
CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The core architecture of CCG1 enables a
base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode multiplex support. CCG1 is also
a Type-C cable ID IC for active and passive cables. The CCG1 controller detects connector insert, plug orientation and VCONN
switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides control signals to manage
external VBUS and VCONN power management solutions and external mux controls for most single cable-docking solutions.
The CCG1 family of devices are fixed-function parts that use a configuration table to control their operation in different applications.
The functionality is implemented in firmware and will be certified against USB Implementers Forum (USB-IF) compliance tests when
available. The programmability allows CCG1 devices to track any USB Specification changes. For information on accessing the source
code, contact Cypress support.
Applications
■ USB Type-C active cables
Features
32-bit MCU Subsystem
■ 48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB
SRAM
Integrated analog blocks
■ 12-bit, 1-Msps ADC for VBUS voltage and current monitoring
■ Dynamic overcurrent and overvoltage protection
Integrated digital blocks
■ Two configurable 16-bit TCPWM blocks
■ One I2C master or slave
Figure 1. CCG1 Block Diagram[2, 3, 4, 5, 6, 7]
Type-C Support
■ Integrated transceiver (BB PHY)
■ Supports up to two USB ports with PD
■ Supports routing of all protocols through an external mux
PD Support
■ Supports Provider and Consumer roles
■ Supports all power profiles
Low-Power Operation
■ 1.8-V to 5.5-V operation
■ Sleep 1.3 mA, Deep Sleep 1.3 A[1]
Packages
■ 35-ball wafer-level CSP (WLCSP)
Notes
1. Values measured for CCG1 silicon only. Application specific power numbers may be higher.
2. Timer, counter, pulse-width modulation block.
3. Serial communication block configurable as I2C.
4. Base band.
5. Termination resistor denoting a Downstream Facing Port (DFP).
6. Termination resistor denoting a Upstream Facing Port (UFP).
7. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA).
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-97904 Rev. **
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 9, 2015
1 page CYPD1104-35FNXIT Datasheet
Table 1. Pin Definitions for 35-ball WLCSP for Active Cable Application (continued)
Functional Pins
Ball Number Type
Description
GPIO_4
C2 I/O General-purpose I/O
GPIO_5
D2 I/O General-purpose I/O
GPIO_6
D6 I/O General-purpose I/O
GPIO_7
E1 I/O General-purpose I/O
GPIO_8
E2 I/O General-purpose I/O
GPIO_9
E3 I/O General-purpose I/O
GPIO_10
E6 I/O General-purpose I/O
Pinouts
Figure 2. 35-Ball WLCSP Pinout
7654321
VCCD
GPIO
CC1_LPRE
F
GPIO
TX_GND
I2C_INT
GPIO
A
VSSA
XRES
TX_M
GPIO
TX_U
I2C_SDA
I2C_SCL
B
VDDD/
VDDA
VCONN_D
ET
CC_VREF
CC1_RX
CC1_LPRX
GPIO
SWD_CLK
C
CC1_TX
GPIO
BYPASS
TX_REF_O
UT
TX_REF_IN
GPIO
SWD_IO
D
ADC_BYPA
SS
GPIO
RA_FAR_D
ISCONNEC
T
RA_DISCO
NNECT
GPIO
GPIO
GPIO
E
Document Number: 001-97904 Rev. **
Page 5 of 19
5 Page CYPD1104-35FNXIT Datasheet
Table 14. Precise Power On Reset (POR)
Spec ID Parameter
SID190
SID192
VFALLPPOR
VFALLDPSLP
Description
BOD trip voltage in active and
sleep modes
BOD trip voltage in Deep Sleep
Min
1.64
1.40
Typ Max Units
Details/Conditions
– – V Guaranteed by characterization
– – V Guaranteed by characterization
SWD Interface
Table 15. SWD Interface Specifications
Spec ID Parameter
Description
SID213 F_SWDCLK1 3.3 V VDDD 5.5 V
SID214 F_SWDCLK2 1.8 V VDDD 3.3 V
SID215 T_SWDI_SETUP T = 1/f SWDCLK
SID216 T_SWDI_HOLD T = 1/f SWDCLK
SID217 T_SWDO_VALID T = 1/f SWDCLK
SID217A T_SWDO_HOLD T = 1/f SWDCLK
Min Typ Max Units
Details/Conditions
–
–
14.00
MHz
SWDCLK ≤ 1/3 CPU clock
frequency
–
–
7.00
MHz
SWDCLK ≤ 1/3 CPU clock
frequency
0.25*T –
– ns Guaranteed by characterization
0.25*T –
– ns Guaranteed by characterization
– – 0.50*T ns Guaranteed by characterization
1 – – ns Guaranteed by characterization
Internal Main Oscillator
Table 16. IMO DC Specifications
(Guaranteed by Design)
Spec ID Parameter
Description
SID218 IIMO1
IMO operating current at 48 MHz
Min
–
Typ Max Units
– 1000.00 µA
Details/Conditions
–
Table 17. IMO AC Specifications
Spec ID Parameter
SID223
SID226
SID229
FIMOTOL1
TSTARTIMO
TJITRMSIMO3
Description
Frequency variation
IMO startup time
RMS Jitter at 48 MHz
Min Typ Max
– – ±2.00
– – 12.00
– 139.00 –
Units
%
µs
ps
Details/Conditions
With API-called calibration
–
–
Internal Low-Speed Oscillator
Table 18. ILO DC Specifications
(Guaranteed by Design)
Spec ID Parameter
SID231 IILO1
SID233 IILOLEAK
Description
ILO operating current at 32 kHz
ILO leakage current
Min
–
–
Typ Max
0.30 1.05
2.00 15.00
Units
µA
nA
Details/Conditions
Guaranteed by characterization
Guaranteed by design
Table 19. ILO AC Specifications
Spec ID Parameter
SID234
SID236
SID237
TSTARTILO1
TILODUTY
FILOTRIM1
Description
ILO startup time
ILO duty cycle
32-kHz trimmed frequency
Min
–
40.00
15.00
Typ
–
50.00
32.00
Max
2.00
60.00
50.00
Units
ms
%
kHz
Details/Conditions
Guaranteed by characterization
Guaranteed by characterization
±60% with trim
Document Number: 001-97904 Rev. **
Page 11 of 19
11 Page |
Páginas | Total 19 Páginas | |
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