|
|
PDF CYPD1121 Data sheet ( Hoja de datos )
| Número de pieza | CYPD1121 | |
| Descripción | USB Type-C Port Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de CYPD1121 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
|
No Preview Available !
CCG1 Datasheet
USB Type-C Port Controller with
Power Delivery
General Description
CCG1 provides a complete USB Type-C and USB Power Delivery port control solution. The core architecture of CCG1 enables a
base Type-C solution that can scale to a complete 100-W USB Power Delivery with Alternate Mode multiplex support. CCG1 is also
a Type-C cable ID IC for active and passive cables. The CCG1 controller detects connector insert, plug orientation and VCONN
switching signals. CCG1 makes it easier to add USB Power Delivery to any architecture because it provides control signals to manage
external VBUS and VCONN power management solutions and external mux controls for most single cable-docking solutions.
The CCG1 family of devices are fixed-function parts that use a configuration table to control their operation in different applications.
The functionality is implemented in firmware and will be certified against USB Implementers Forum (USB-IF) compliance tests when
available. The programmability allows CCG1 devices to track any USB Specification changes. For information on accessing the source
code, contact Cypress support.
Applications
■ Notebooks, tablets, monitors, docking stations
■ Power adapters, USB Type-C cables
Features
32-bit MCU Subsystem
■ 48-MHz ARM Cortex-M0 CPU with 32-KB flash and 4-KB
SRAM
Integrated analog blocks
■ 12-bit, 1-Msps ADC for VBUS voltage and current monitoring
■ Dynamic overcurrent and overvoltage protection
Integrated digital blocks
■ Two configurable 16-bit TCPWM blocks
■ One I2C master or slave
Figure 1. CCG1 Block Diagram[2, 3, 4, 5, 6, 7]
Type-C Support
■ Integrated transceiver (BB PHY)
■ Supports up to two USB ports with PD
■ Supports routing of all protocols through an external mux
PD Support
■ Supports Provider and Consumer roles
■ Supports all power profiles
Low-Power Operation
■ 3.2 V to 5.5 V operation
■ Sleep 1.3 mA, Deep Sleep 1.3 A[1]
Packages
■ 40-pin QFN
■ 16-pin SOIC
■ 35-ball wafer-level CSP (WLCSP)
Notes
1. Values measured for CCG1 silicon only. Application specific power numbers may be higher.
2. Timer, counter, pulse-width modulation block.
3. Serial communication block configurable as I2C.
4. Base band.
5. Termination resistor denoting a Downstream Facing Port (DFP).
6. Termination resistor denoting a Upstream Facing Port (UFP).
7. Termination resistor denoting an Electronically Marked Cable Assembly (EMCA).
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-93639 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised October 3, 2016
1 page  
CCG1 Datasheet
Table 2 provides the pin definitions for 40-pin QFN and 35-ball WLCSP for the notebook, tablet, smartphone, and monitor
applications. Refer to Table 23 on page 23 for part numbers to package mapping.
Table 2. Pin Definitions for 40-QFN and 35-ball WLCSP for Notebook, Tablet, SmartPhone and Monitor Applications
Functional Pins
MUXSEL_1
MUXSEL_2
CYPD
CYPD
CYPD
112P2i-n4s0[L8Q] XI 112P1i-n4s0[L9Q] XI 113B1a-3ll5sF[1N0]XIT
1 1 D5
2 2 D6
CC1_CTRL
3 3 D3
CC2_CTRL
MUXSEL_3
MUXSEL_4
CS_P
CS_M
VSS
CC1
CC_SEL_REF_1
SWD_IO
SWD_CLK
HOTPLUG_DET
GPIO1
VSEL2
GPIO2
GPIO3
4
5
6
7
8
9
10
11
12
13
14
15
–
16
17
4
5
6
7
8
9
10
11
12
13
14
–
15
–
–
E4
E5
E6
E3
E2
–
-
E1
D1
C1
C2
–
–
–
–
Type
O
O
I/O
I/O
O
O
I
I
GND
I/O
O
I/O
I
I/O
I/O
O
I/O
I/O
Description
External Data Mux Select signal 1
External Data Mux Select signal 2
CC1 control
0: TX enabled
z: RX sense
CC2 control
0: TX enabled
z: RX sense
External Data Mux Select signal 3
External Data Mux Select signal 4
Current Sensing Plus input
Current Sensing Minus input I
Ground
Configuration Channel 1
CC Reference Select signal
SWD IO
SWD Clock
HotPlug Detection for Display Port Alternate Mode
General-purpose I/O
Voltage Select signal 2 for selecting output voltage
General-purpose I/O
General-purpose I/O
IFAULT
Current Fault Indication
– 17 – I 0: No fault
1: Current fault
I2C_SCL
I2C_SDA
I2C_INT
18 18
19 19
20 20
B1 I/O I2C Clock signal
B2 I/O I2C Data signal
A2 O I2C Interrupt
CC_SEL_REF_2
21
21
A1 O CC Reference Select signal
CC1_RD
CC1_RP
22 22
23 23
Open Drain signal to connect RD to CC 1 line
C3
O
z: RD not connected
0: RD connected for Monitor application
1: RD connected for Notebook application
Open Source signal to connect RP to CC 1 line
A5 O z: RP not connected
1: RP connected
Notes
8. Pinout for Notebook DRP application for 40-QFN.
9. Pinout for Monitor DRP application for 40-QFN.
10. Pinout for Notebook DRP application for 35-CSP.
Document Number: 001-93639 Rev. *J
Page 5 of 31
5 Page 
CCG1 Datasheet
Figure 5. Pinout for CYPD1103-35FNXIT/CYPD1131-FNXIT
7654321
VCCD
GPIO/
CC2_RD
CC1_LPRE
F/CC1_RP
GPIO/
CC1_VCO
NN_CTRL
TX_GND/
VBUS_DIS
CHARGE
GPIO/
I2C_INT
GPIO/
CC_SEL_R
EF_2
A
VSSA
XRES
TX_M/
CC2_VCON
N_CTRL
GPIO/
CC2_RP
TX_U/
CC2
I2C_SDA
I2C_SCL
B
VDDD/
VDDA
VCONN_D
ET/
CC_SEL_R
EF_3
CC_VREF/
VBUS_VRE
F
CC1_RX/
VBUS_VMO
N
CC1_LPRX /
CC1_RD
GPIO/
HOTPLUG_
DET
SWD_CLK
C
CC1_TX/
VBUS_C_C
TRL
GPIO/
MUXSEL_2
BYPASS/
MUXSEL_1
TX_REF_O
UT/
CC_VREF
TX_REF_IN
/CC1_CTRL
GPIO
SWD_IO
D
GPIO/
VBUS_P_C
TRL
GPIO/
MUXSEL_4
RA_FAR_D
ISCONNEC
T/
MUXSEL_3
RA_DISCO
NNECT/
CC2_CTRL
GPIO/
CS_P
GPIO/
CS_M
GPIO/
CC_SEL_R
EF_1
E
Power
The following power system diagram shows the minimum set of
power supply pins as implemented for the CCG1. The system
has one regulator in Active mode for the digital circuitry. There is
no analog regulator; the analog circuits run directly from the
VDDA input. There is a separate regulator for the Deep Sleep
mode. There is a separate low-noise regulator for the bandgap.
The supply voltage range is 3.2 V to 5.5 V with all functions and
circuits operating over that range.
VDDA and VDDD must be shorted together; the grounds, VSSA
and VSS must also be shorted together. Bypass capacitors must
be used from VDDD to ground. The typical practice for systems
in this frequency range is to use a capacitor in the 1-µF range in
parallel with a smaller capacitor (0.1 µF, for example). Note that
these are simply rules of thumb and that, for critical applications,
the PCB layout, lead inductance, and the bypass capacitor
parasitic should be simulated to design and obtain optimal
bypassing.
Refer to Application Diagrams for bypassing schemes.
Document Number: 001-93639 Rev. *J
Page 11 of 31
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CYPD1121.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| CYPD1120 | USB Power Delivery Alternate Mode Controller on Type-C | Cypress Semiconductor |
| CYPD1121 | USB Type-C Port Controller | Cypress Semiconductor |
| CYPD1122 | USB Type-C Port Controller | Cypress Semiconductor |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
 Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |