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CYPD2122 の電気的特性と機能

CYPD2122のメーカーはCypress Semiconductorです、この部品の機能は「Type-C Port Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 CYPD2122
部品説明 Type-C Port Controller
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CYPD2122 Datasheet, CYPD2122 PDF,ピン配置, 機能
EZ-PD™ CCG2 Datasheet
USB Type-C Port Controller
USB Type-C Port Controller
General Description
EZ-PD™ CCG2 is a USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG2 provides a
complete USB Type-C and USB Power Delivery port control solution for passive cables, active cables, and powered accessories. It
can also be used in many upstream and downstream facing port applications. EZ-PD CCG2 uses Cypress’s proprietary M0S8
technology with a 32-bit, 48-MHz ARM® Cortex®-M0 processor with 32-KB flash and integrates a complete Type-C Transceiver
including the Type-C termination resistors RP, RD and RA.
Applications
Type-C Support
USB Type-C EMCA cables
USB Type-C powered accessories
USB Type-C upstream facing ports
USB Type-C downstream facing ports
Features
Integrated transceiver (baseband PHY)
Integrated UFP (RD), EMCA (RA) termination resistors, and
current sources for DFP (RP)
Supports one USB Type-C port
Low-Power Operation
2.7-V to 5.5-V operation
32-bit MCU Subsystem
48-MHz ARM Cortex-M0 CPU
32-KB Flash
4-KB SRAM
In-system reprogrammable
Integrated Digital Blocks
Integrated timers and counters to meet response times
required by the USB-PD protocol
Run-time reconfigurable serial communication block (SCB)
with reconfigurable I2C, SPI, or UART functionality
Clocks and Oscillators
Integrated oscillator eliminating the need for external clock
Two independent VCONN rails with integrated isolation
between the two
Independent supply voltage pin for GPIO that allows 1.71-V to
5.5-V signaling on the I/Os
Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.0 mA
System-Level ESD on CC and VCONN Pins
± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
Packages
1.63 mm × 2.03 mm, 20-ball wafer-level CSP (WLCSP) with
0.4-mm ball pitch
2.5 mm × 3.5 mm × 0.6 mm 14-pin DFN
4.0 mm × 4.0 mm, 0.55 mm 24-pin QFN
Supports industrial (40 °C to +85 °C) and extended industrial
(40 °C to +105 °C) temperature ranges
Logic Block Diagram
CCG2: USB Type-C Cable Controller
MCU Subsystem
Integrated Digital Blocks
TCPWM1
CORTEX-M0
48 MHz
SCB2
(I2C, SPI, UART)
SCB2
(I2C, SPI, UART)
Profiles and
Configurations
I/O Subsystem
CC5
VCONN1
VCONN2
VDDIO
GPIO6
Port
Flash
(32 KB)
SRAM
(4 KB)
Baseband MAC
Baseband PHY
Integrated Rd3, Ra4,
and Rp7
Serial Wire Debug
1 Timer, counter, pulse-width modulation block
2 Serial communication block configurable as UART, SPI, or I2C
3 Termination resistor denoting a UFP
4 Termination resistor denoting an EMCA
5 Configuration Channel
6 General-purpose input/output
7 Current Sources to indicate a DFP
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-93912 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 2, 2016

1 Page





CYPD2122 pdf, ピン配列
EZ-PD™ CCG2 Datasheet
Contents
Functional Overview .........................................................4
CPU and Memory Subsystem .....................................4
USB-PD Subsystem (SS) ............................................5
System Resources .......................................................5
Peripherals ..................................................................6
GPIO ............................................................................6
Pinouts ...............................................................................7
Power .................................................................................9
Application Diagrams .....................................................10
Electrical Specifications .................................................17
Absolute Maximum Ratings .......................................17
Device Level Specifications .......................................18
Digital Peripherals ......................................................20
Memory ......................................................................22
System Resources .....................................................23
Ordering Information ......................................................26
Ordering Code Definitions .........................................26
Packaging ........................................................................27
Acronyms ........................................................................29
Document Conventions .................................................30
Units of Measure .......................................................30
References and Links To Applications Collaterals ....31
Document History Page .................................................32
Sales, Solutions, and Legal Information ......................33
Worldwide Sales and Design Support .......................33
Products ....................................................................33
PSoC® Solutions .......................................................33
Cypress Developer Community .................................33
Technical Support ......................................................33
Document Number: 001-93912 Rev. *L
Page 3 of 33


3Pages


CYPD2122 電子部品, 半導体
EZ-PD™ CCG2 Datasheet
Peripherals
Serial Communication Blocks (SCB)
EZ-PD CCG2 has two SCBs, which can be configured to
implement an I2C, SPI, or UART interface. The hardware I2C
blocks implement full multi-master and slave interfaces capable
of multimaster arbitration. In the SPI mode, the SCB blocks can
be configured to act as master or slave.
In the I2C mode, the SCB blocks are capable of operating at
speeds of up to 1 Mbps (Fast Mode Plus) and have flexible
buffering options to reduce interrupt overhead and latency for the
CPU. These blocks also support I2C that creates a mailbox
address range in the memory of EZ-PD CCG2 and effectively
reduce I2C communication to reading from and writing to an
array in memory. In addition, the blocks support 8-deep FIFOs
for receive and transmit which, by increasing the time given for
the CPU to read data, greatly reduce the need for clock
stretching caused by the CPU not having read data on time.
The I2C peripherals are compatible with the I2C Standard-mode,
Fast-mode, and Fast-mode Plus devices as defined in the NXP
I2C-bus specification and user manual (UM10204). The I2C bus
I/Os are implemented with GPIO in open-drain modes.
The I2C port on SCB 1 block of EZ-PD CCG2 is not completely
compliant with the I2C spec in the following respects:
The GPIO cells for SCB 1's I2C port are not overvoltage-tolerant
and, therefore, cannot be hot-swapped or powered up
independently of the rest of the I2C system.
Fast-mode Plus has an IOL specification of 20 mA at a VOL of
0.4 V. The GPIO cells can sink a maximum of 8-mA IOL with a
VOL maximum of 0.6 V.
Fast-mode and Fast-mode Plus specify minimum Fall times,
which are not met with the GPIO cell; Slow strong mode can
help meet this spec depending on the bus load.
Timer/Counter/PWM Block (TCPWM)
EZ-PD CCG2 has six TCPWM blocks. Each implements a 16-bit
timer, counter, pulse-width modulator (PWM), and quadrature
decoder functionality. The block can be used to measure the
period and pulse width of an input signal (timer), find the number
of times a particular event occurs (counter), generate PWM
signals, or decode quadrature signals.
GPIO
EZ-PD CCG2 has up to 10 GPIOs in addition to the I2C and SWD
pins, which can also be used as GPIOs. The I2C pins from SCB
0 are overvoltage-tolerant. The number of available GPIOs vary
with the package. The GPIO block implements the following:
Seven drive strength modes:
Input only
Weak pull-up with strong pull-down
Strong pull-up with weak pull-down
Open drain with strong pull-down
Open drain with strong pull-up
Strong pull-up with strong pull-down
Weak pull-up with weak pull-down
Input threshold select (CMOS or LVTTL)
Individual control of input and output buffer enabling/disabling
in addition to the drive strength modes
Hold mode for latching previous state (used for retaining I/O
state in Deep Sleep mode)
Selectable slew rates for dV/dt related noise control to improve
EMI
During power-on and reset, the I/O pins are forced to the disable
state so as not to crowbar any inputs and/or cause excess
turn-on current. A multiplexing network known as a high-speed
I/O matrix is used to multiplex between various signals that may
connect to an I/O pin.
Document Number: 001-93912 Rev. *L
Page 6 of 33

6 Page



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共有リンク

Link :


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