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PDF CYPD2120 Data sheet ( Hoja de datos )
| Número de pieza | CYPD2120 | |
| Descripción | Type-C Port Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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EZ-PD™ CCG2 Datasheet
USB Type-C Port Controller
USB Type-C Port Controller
General Description
EZ-PD™ CCG2 is a USB Type-C controller that complies with the latest USB Type-C and PD standards. EZ-PD CCG2 provides a
complete USB Type-C and USB Power Delivery port control solution for passive cables, active cables, and powered accessories. It
can also be used in many upstream and downstream facing port applications. EZ-PD CCG2 uses Cypress’s proprietary M0S8
technology with a 32-bit, 48-MHz ARM® Cortex®-M0 processor with 32-KB flash and integrates a complete Type-C Transceiver
including the Type-C termination resistors RP, RD and RA.
Applications
Type-C Support
■ USB Type-C EMCA cables
■ USB Type-C powered accessories
■ USB Type-C upstream facing ports
■ USB Type-C downstream facing ports
Features
■ Integrated transceiver (baseband PHY)
■ Integrated UFP (RD), EMCA (RA) termination resistors, and
current sources for DFP (RP)
■ Supports one USB Type-C port
Low-Power Operation
■ 2.7-V to 5.5-V operation
32-bit MCU Subsystem
■ 48-MHz ARM Cortex-M0 CPU
■ 32-KB Flash
■ 4-KB SRAM
■ In-system reprogrammable
Integrated Digital Blocks
■ Integrated timers and counters to meet response times
required by the USB-PD protocol
■ Run-time reconfigurable serial communication block (SCB)
with reconfigurable I2C, SPI, or UART functionality
Clocks and Oscillators
■ Integrated oscillator eliminating the need for external clock
■ Two independent VCONN rails with integrated isolation
between the two
■ Independent supply voltage pin for GPIO that allows 1.71-V to
5.5-V signaling on the I/Os
■ Reset: 1.0 µA, Deep Sleep: 2.5 µA, Sleep: 2.0 mA
System-Level ESD on CC and VCONN Pins
■ ± 8-kV Contact Discharge and ±15-kV Air Gap Discharge based
on IEC61000-4-2 level 4C
Packages
■ 1.63 mm × 2.03 mm, 20-ball wafer-level CSP (WLCSP) with
0.4-mm ball pitch
■ 2.5 mm × 3.5 mm × 0.6 mm 14-pin DFN
■ 4.0 mm × 4.0 mm, 0.55 mm 24-pin QFN
■ Supports industrial (40 °C to +85 °C) and extended industrial
(40 °C to +105 °C) temperature ranges
Logic Block Diagram
CCG2: USB Type-C Cable Controller
MCU Subsystem
Integrated Digital Blocks
TCPWM1
CORTEX-M0
48 MHz
SCB2
(I2C, SPI, UART)
SCB2
(I2C, SPI, UART)
Profiles and
Configurations
I/O Subsystem
CC5
VCONN1
VCONN2
VDDIO
GPIO6
Port
Flash
(32 KB)
SRAM
(4 KB)
Baseband MAC
Baseband PHY
Integrated Rd3, Ra4,
and Rp7
Serial Wire Debug
1 Timer, counter, pulse-width modulation block
2 Serial communication block configurable as UART, SPI, or I2C
3 Termination resistor denoting a UFP
4 Termination resistor denoting an EMCA
5 Configuration Channel
6 General-purpose input/output
7 Current Sources to indicate a DFP
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-93912 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised August 2, 2016
1 page  
EZ-PD™ CCG2 Datasheet
USB-PD Subsystem (SS)
EZ-PD CCG2 has a USB-PD subsystem consisting of a USB
Type-C baseband transceiver and physical-layer logic. This
transceiver performs the BMC and the 4b/5b encoding and
decoding functions as well as the 1.2-V front end. This
subsystem integrates the required termination resistors to
identify the role of the EZ-PD CCG2 solution. RA is used to
identify EZ-PD CCG2 as an accessory or an electronically
marked cable. RD is used to identify EZ-PD CCG2 as a UFP in
a hybrid cable or a dongle. When configured as a DFP, integrated
current sources perform the role of RP or pull-up resistors. These
current sources can be programmed to indicate the complete
range of current capacity on VBUS defined in the Type-C spec.
EZ-PD CCG2 responds to all USB-PD communication. The
EZ-PD CCG2 USB-PD sub-system can be configured to
respond to SOP, SOP', or SOP” messaging.
The USB-PD sub-system contains a 8-bit SAR (Successive
Approximation Register) ADC for analog to digital conversions.
The ADC includes a 8-bit DAC and a comparator. The DAC
output forms the positive input of the comparator. The negative
input of the comparator is from a 4-input multiplexer. The four
inputs of the multiplexer are a pair of global analog multiplex
busses an internal bandgap voltage and an internal voltage
proportional to the absolute temperature. All GPIO inputs can be
connected to the global Analog Multiplex Busses through a
switch at each GPIO that can enable that GPIO to be connected
to the mux bus for ADC use. The CC1, CC2 and RD1 pins are
not available to connect to the mux busses.
Figure 2. USB-PD Subsystem
To/From system Resources
vref iref VDDD
To/ from AHB
From AMUX
Ra Enable
VConn1 detect
VConn2 detect
TxRx Enable
8-bit ADC
VCONN power logic
Enable
Logic
VCONN
Detect
Ra
Ra
VDDD
VCONN1
VCONN2
8kV IEC ESD
Tx_data
from AHB
Tx
SRAM
Rx_data
to AHB
Rx
SRAM
CRC
4b5b
Encoder
4b5b
Decoder
Digital Baseband PHY
SOP
Insert
BMC
Encoder
SOP
Detect
BMC
Decoder
CC control
CC detect
Deep Sleep Reference Enable
Functional, Wakeup Interrupts
Deep Sleep
Vref & Iref Gen
vref, iref
Enable Logic
TX
RX
Rp
Comp
Ref
Active
Rd
Analog Baseband PHY
CC1
RD1
CC2
DB 8kV IEC ESD
Rd
System Resources
Power System
The power system is described in detail in the section Power on
page 9. It provides assurance that voltage levels are as required
for each respective mode and either delay mode entry (on
power-on reset (POR), for example) until voltage levels are as
required for proper function or generate resets (Brown-Out
Detect (BOD)) or interrupts (Low Voltage Detect (LVD)). EZ-PD
CCG2 can operate from three different power sources over the
range of 2.7 to 5.5 V and has three different power modes,
transitions between which are managed by the power system.
EZ-PD CCG2 provides Sleep and Deep Sleep low-power
modes.
Clock System
The clock system for EZ-PD CCG2 consists of the Internal Main
Oscillator (IMO) and the Internal Low-power Oscillator (ILO).
Document Number: 001-93912 Rev. *L
Page 5 of 33
5 Page 
EZ-PD™ CCG2 Datasheet
Type-C
Plug
VCONN
Figure 8. Passive EMCA Application – Single EZ-PD CCG2 Per Plug
VBUS
Type-C
Plug
VCONN
0.1uF
1uF
VDDIO
4.7k
1uF
E3
E4 VDDD
VCONN1
E1
VDDIO
C4
VCONN2
C3
GPIO
A1
VCCD
B1
XRES
D4 VSS
CCG2
D3
GPIO
C2
GPIO
D2
GPIO
B2
GPIO
A4
CC2
CC1 B4
C1 VSS
B3
RD1
I2C_0 I2C_0
_SCL _SDA
A3 A2
SWD_ SWD_
IO CLK
E2 D1
1uF
VDDIO
4.7k
1uF
E3
C4 VDDD
VCONN2
E1
VDDIO
E4
VCONN1
C3
GPIO
A1
VCCD
D3
GPIO
C2
GPIO
D2
GPIO
B1
XRES
D4 VSS
CCG2
B2
GPIO
A4
CC2
CC1 B4
C1 VSS
B3
RD1
I2C_0 I2C_0
_SCL _SDA
A3 A2
SWD_ SWD_
IO CLK
E2 D1
0.1uF
CC
SuperSpeed and HighSpeed Lines
GND
Figure 9 shows a CCG2 device being used in a UFP application (tablet with a Type-C port) only as a power consumer.
The Type-C receptacle brings in HighSpeed and SuperSpeed lines, which are connected directly to the applications processor. The
VBUS line from the Type-C receptacle goes directly to the UFP (tablet) charger circuitry. The applications processor communicates
over the I2C signal with the CCG2 device, and the CC1 and CC2 lines from the Type-C receptacle are connected directly to the
respective CC1/2 pins of the CCG2 device.
Figure 9. Upstream Facing Port (UFP) Application – Tablet with a Type-C Port
Charger
VBUS
1.8 V
4.7 kΩ
Application
Processor
4.7 kΩ
INT
5.0 V
1.8 V
1 uF
E3
C4 VDDD
VCONN2
1 uF
E1
VDDIO
GPIO D3
E4
VCONN1
E2
SWD_IO
GPIO C2
D2
GPIO
D1
SWD_CLK
C3 GPIO
CCG2
B2
GPIO
CC2 A4
A3 I2C_0_SCL
A2 I2C_0_SDA
CC1 B4
B3
RD1
390 pF 390 pF
VSS
D4
VSS
C1
VCCD
A1
1 uF
XRES
B1
4.7 kΩ
1.8 V
Type-C
Receptacle
HighSpeed Lines
Application
Processor/
Graphics
Controller
SuperSpeed Lines
Document Number: 001-93912 Rev. *L
Page 11 of 33
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CYPD2120.PDF ] | |
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