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PDF CYUSB2014 Data sheet ( Hoja de datos )
| Número de pieza | CYUSB2014 | |
| Descripción | SuperSpeed USB Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYUSB301X/CYUSB201X
EZ-USB® FX3: SuperSpeed USB Controller
EZ-USB® FX3: SuperSpeed USB Controller
Features
■ Universal serial bus (USB) integration
❐ USB 3.1, Gen 1 and USB 2.0 peripherals compliant with USB
3.1 Specification Revision 1.0 (TID # 340800007)
❐ 5-Gbps SuperSpeed PHY compliant with USB 3.1 Gen 1
❐ High-speed On-The-Go (HS-OTG) host and peripheral
compliant with OTG Supplement Version 2.0
❐ Thirty-two physical endpoints
❐ Support for battery charging Specification 1.1 and accessory
charger adaptor (ACA) detection
■ General Programmable Interface (GPIF™ II)
❐ Programmable 100-MHz GPIF II enables connectivity to a
wide range of external devices
❐ 8-, 16-, 24-, and 32-bit data bus
❐ Up to16 configurable control signals
■ Fully accessible 32-bit CPU
❐ ARM926EJ core with 200-MHz operation
❐ 512-KB or 256-KB embedded SRAM
■ Additional connectivity to the following peripherals
❐ SPI master at up to 33 MHz
❐ UART support of up to 4 Mbps
❐ I2C master controller at 1 MHz
❐ I2S master (transmitter only) at sampling frequencies of
32 kHz, 44.1 kHz, and 48 kHz
■ Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on and 20 µA with VBATT off
■ Independent power domains for core and I/O
❐ Core operation at 1.2 V
❐ I2S, UART, and SPI operation at 1.8 to 3.3 V
❐ I2C operation at 1.2 V to 3.3 V
■ Package options
❐ 121-ball, 10- × 10-mm, 0.8-mm pitch Pb-free ball grid array
(BGA)
❐ 131-ball, 4.7- × 5.1-mm, 0.4-mm pitch wafer-level chip scale
package (WLCSP)
❐ See Table 20 for details on the eight FX3 variants
■ EZ-USB® Software Development Kit (SDK) for code devel-
opment of firmware and PC Applications
❐ Includes RTOS Framework (using ThreadX Version 5)
❐ Firmware examples covering all I/O modules
❐ Visual Studio host examples using C++ and C#
■ SuperSpeed Explorer Board available for rapid prototyping
❐ Several accessory boards also available:
• Adapter boards for Xilinx/Altera FPGA development
• Adapter board for Video development
• CPLD board for concept testing and initial development
Applications
■ Digital video camcorders
■ Digital still cameras
■ Printers
■ Scanners
■ Video capture cards
■ Test and measurement equipment
■ Surveillance cameras
■ Personal navigation devices
■ Medical imaging devices
■ Video IP phones
■ Portable media players
■ Industrial cameras
■ Data loggers
■ Data acquisition
■ High-performance Human Interface Devices (gesture
recognition)
Functional Description
For a complete list of related documentation, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-52136 Rev. *T
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 29, 2016
1 page  
CYUSB301X/CYUSB201X
Functional Overview
Cypress’s EZ-USB FX3 is a SuperSpeed peripheral controller,
providing integrated and flexible features.
FX3 has a fully configurable, parallel, general programmable
interface called GPIF II, which can connect to any processor,
ASIC, or FPGA. GPIF II is an enhanced version of the GPIF in
FX2LP, Cypress’s flagship USB 2.0 product. It provides easy and
glueless connectivity to popular interfaces, such as
asynchronous SRAM, asynchronous and synchronous address
data multiplexed interfaces, and parallel ATA.
FX3 has integrated the USB 3.1 Gen 1 and USB 2.0 physical
layers (PHYs) along with a 32-bit ARM926EJ-S microprocessor
for powerful data processing and for building custom
applications. It implements an architecture that enables
375-MBps data transfer from GPIF II to the USB interface.
An integrated USB 2.0 OTG controller enables applications in
which FX3 may serve dual roles; for example, EZ-USB FX3 may
function as an OTG Host to MSC as well as HID-class devices.
FX3 contains 512 KB or 256 KB of on-chip SRAM (see Ordering
Information on page 45) for code and data. EZ-USB FX3 also
provides interfaces to connect to serial peripherals such as
UART, SPI, I2C, and I2S.
FX3 comes with application development tools. The software
development kit comes with firmware and host application
examples for accelerating time to market.
FX3 complies with the USB 3.1, Gen 1.0 specification and is also
backward compatible with USB 2.0. It also complies with the
Battery Charging Specification v1.1 and USB 2.0 OTG
Specification v2.0.
Application Examples
In a typical application (see Figure 1), the FX3 functions as the
main processor running the application software that connects
external hardware to the SuperSpeed USB connection.
Additionally, FX3 can function as a coprocessor connecting via
the GPIF II interface to an application processor (see Figure 2)
and operates as a subsystem providing SuperSpeed USB
connectivity to the application processor.
Figure 1. EZ-USB FX3 as Main Processor
Crystal*
Clock
USB
Host
USB
Ez-USB FX3
GPIF II
I2C
* A clock input may be provided on the
CLKIN pin instead of a crystal input
EEPROM
External Slave
Device
(e.g. Image
Sensor)
Document Number: 001-52136 Rev. *T
Page 5 of 54
5 Page 
CYUSB301X/CYUSB201X
Power
FX3 has the following power supply domains:
■ IO_VDDQ: This is a group of independent supply domains for
digital I/Os. The voltage level on these supplies is 1.8 V to 3.3 V.
FX3 provides six independent supply domains for digital I/Os
listed as follows (see Table 7 on page 15 for details on each of
the power domain signals):
❐ VIO1: GPIF II I/O
❐ VIO2: IO2
❐ VIO3: IO3
❐ VIO4: UART-/SPI/I2S
❐ VIO5: I2C and JTAG (supports 1.2 V to 3.3 V)
❐ CVDDQ: This is the supply voltage for clock and reset I/O. It
should be either 1.8 V or 3.3 V based on the voltage level of
the CLKIN signal.
❐
sVuDpDp:lTyh-visolitsatghee
supply voltage for the logic core. The nominal
level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
• AVDD: This is the 1.2-V supply for the PLL, crystal oscilla-
tor, and other core analog circuits
• U3TXVDDQ/U3RXVDDQ: These are the 1.2-V supply volt-
ages for the USB 3.0 interface.
■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply
for the USB I/O and analog circuits. This supply powers the
USB transceiver through FX3's internal voltage regulator.
VBATT is internally regulated to 3.3 V.
Power Modes
FX3 supports the following power modes:
■ Normal mode: This is the full-functional operating mode. The
internal CPU clock and the internal PLLs are enabled in this
mode.
❐ Normal operating power consumption does not exceed the
s1u5mfoorfcIuCrCreCnotrceomnsauxmapntdioInCCspUeScBifimcaatixo(nsse)e. Table 7 on page
❐ The I/O power supplies VIO2, VIO3, VIO4, and VIO5 can be
turned off when the corresponding interface is not in use.
VIO1 cannot be turned off at any time if the GPIF II interface
is used in the application.
■ Low-power modes (see Table 6 on page 11):
❐ Suspend mode with USB 3.0 PHY enabled (L1)
❐ Suspend mode with USB 3.0 PHY disabled (L2)
❐ Standby mode (L3)
❐ Core power-down mode (L4)
Table 6. Entry and Exit Methods for Low-Power Modes
Low-Power Mode
Characteristics
Methods of Entry
Methods of Exit
Suspend Mode with ■ The power consumption in this mode does ■ Firmware executing on
■ D+ transitioning to low
USB 3.0 PHY
Enabled (L1)
not exceed ISB1
ARM926EJ-S core can put FX3 into or high
■ USB 3.0 PHY is enabled and is in U3 mode
(one of the suspend modes defined by the
USB 3.0 specification). This one block
alone is operational with its internal clock
while all other clocks are shut down
suspend mode. For example, on
USB suspend condition, firmware
may decide to put FX3 into suspend
mode
■ External Processor, through the use
■ D- transitioning to low
or high
■ Impedance change on
OTG_ID pin
■ All I/Os maintain their previous state
of mailbox registers, can put FX3 into ■ Resume condition on
suspend mode
SSRX±
■ Power supply for the wakeup source and
core power must be retained. All other
■ Detection of VBUS
power domains can be turned on/off
individually
■ Level detect on
UART_CTS
■ The states of the configuration registers,
buffer memory, and all internal RAM are
(programmable
polarity)
maintained
■ GPIF II interface
■ All transactions must be completed before
assertion of CTL[0]
FX3 enters Suspend mode (state of
outstanding transactions are not
■ Assertion of RESET#
preserved)
■ The firmware resumes operation from
where it was suspended (except when
woken up by RESET# assertion) because
the program counter does not reset
Document Number: 001-52136 Rev. *T
Page 11 of 54
11 Page | ||
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| PDF Descargar | [ Datasheet CYUSB2014.PDF ] | |
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