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PDF CYUSB2025 Data sheet ( Hoja de datos )
| Número de pieza | CYUSB2025 | |
| Descripción | USB and Mass Storage Peripheral Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYUSB202X
SD2™ USB and Mass Storage Peripheral Controller
Features
■ Latest-generation storage support
❐ SD2.0/SDXC – UHS1 SDR50 / DDR50 Master
❐ eMMC 4.4 Master
❐ SDIO 3.0 Master
■ USB integration
❐ Certified USB 2.0 peripheral: Hi-Speed (HS), and Full-Speed
(FS) only)
❐ Thirty-two physical endpoints
❐ Integrated transceiver
❐ Accessory charger adaptor (ACA) support
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on and 20 µA with VBATT off
■ I2C master controller at 1 MHz
■ Selectable input clock frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
■ Independent power domains for core and I/O
■ 10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package
Applications
■ USB thumb drives
■ Card readers
■ Laptop with SD slots
■ SD slot in TV/STB
■ WiFi Dongles
Logic Block Diagram
FSLC[0]
FSLC[1]
FSLC[2]
CLKIN
CLKIN_32
XTALIN
XTALOUT
JTAG
ARM926EJ-S
Embedded
SRAm
(512 kB/
256 KB)
GPIOs
USB
EPs
HS/FS
Peripheral
UART
SPI
I2C I2S
SDIO/SD/MMC Controller
S0-PORT
S1-PORT
D+
D-
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-87710 Rev. *B
• San Jose, CA 95134-1709 • 408-943-2600
Revised June 29, 2016
1 page  
CYUSB202X
Power
SD2 has the following main groups of power supply domains:
■ IO_VDDQ: This refers to a group of independent supply
domains for digital I/Os. The voltage level on these supplies
are 1.8 V to 3.3 V. SD2 provides six independent supply
domains for digital I/Os listed as follows:
❐ VIO2: S0-Port (for SD/MMC) I/O Power Supply Domain
❐ VIO3: S1-Port (for SD/MMC) I/O Power Supply Domain
❐ VIO1: S2-Port (GPIO) Power Supply Domain
❐ VIO4: S1-Port GPIO[53:57]/O Power Supply Domain (these
pins support MMC’s high nibble data line - D[7:4] on S1-Port)
❐ VIO5: I2C Power Supply Domain (supports 1.2 V to 3.3 V)
❐ CVDDQ: Clock Power Supply Domain
■ VDD: This is the supply voltage for the logic core. The nominal
supply voltage level is 1.2 V. This supplies the core logic
circuits. The same supply must also be used for the following:
❐ AVDD: This is the 1.2-V supply for the PLL, crystal oscillator
and other core analog circuits
■ VBATT/VBUS: This is the 3.2-V to 6-V battery power supply
for the USB I/O and analog circuits. This supply powers the
USB transceiver through SD2’s internal voltage regulator.
VBATT is internally regulated to 3.3 V.
Power Modes
SD2 supports the following power modes:
■ Normal mode: This is the full-functional operating mode. In this
mode the internal CPU clock and the internal PLLs are enabled.
Normal operating power consumption does not exceed the sum
of ICC_CORE max and ICC_USB max (see Table 8 on page 12
for current consumption specifications).
The I/O power supplies (VIO2, VIO3, VIO4, and VIO5) may be
turned off when the corresponding interface is not in use.
S2VDDQ cannot be turned off at any time if the S2-Port is used
in the application.
■ SD2 supports four low-power modes (see Table 6 on page 5):
❐ Suspend mode with USB 2.0 PHY enabled (L1 mode)
❐ Suspend mode with USB 2.0 PHY disabled (L2 mode)
❐ Standby mode (L3 mode)
❐ Core power-down mode (L4 mode)
Table 6. Entry and Exit Methods for Low-Power Modes
Low Power Mode
Suspend mode with
USB 2.0 PHY
Enabled (L1 mode)
Characteristics
Methods of Entry
Methods of Exit
■ The power consumption in this ■ Firmware executing on the core can ■ D+ transitioning to low or high
mode does not exceed ISB1
■ USB 2.0 PHY is enabled and is in
U3 mode (one of the suspend
modes defined by the USB 3.0
specification). This one block
alone operates with its internal
put SD2 into suspend mode. For
example, on USB suspend
condition, firmware may decide to
put SD2 into suspend mode
■ D– transitioning to low or high
■ Resume condition on SSRX +/-
■ Detection of VBUS
■ Assertion of GPIO[17]
clock while all other clocks are
shut down
■ Assertion of RESET#
■ All I/Os maintain their previous
state
■ Power supply for the wakeup
source and core power must be
retained. All other power domains
can be turned on/off individually
■ The states of the configuration
registers, buffer memory and all
internal RAM are maintained
■ All transactions must be
completed before SD2 enters
Suspend mode (state of
outstanding transactions are not
preserved)
■ The firmware resumes operation
from where it was suspended
(except when woken up by
RESET# assertion) because the
program counter does not reset
Document Number: 001-87710 Rev. *B
Page 5 of 27
5 Page 
CYUSB202X
Table 7. Pin List (continued)
Pin Power
No. Domain I/O
E10 PWR
B10 PWR
A1 PWR
E11 PWR
D8 PWR
H11 PWR
E2 PWR
L9 PWR
G1 PWR
F1 PWR
G11 PWR
E3 PWR
L1 PWR
B1 PWR
L6 PWR
B6 PWR
B5
A2
C11 PWR
L11 PWR
A7 PWR
B7 PWR
C3 PWR
B8 PWR
E9 PWR
B9 PWR
F11 PWR
H1 PWR
L7 PWR
J11 PWR
L5 PWR
K4 PWR
L3 PWR
K3 PWR
L2 PWR
A8 PWR
Name
VBATT
VDD
VSS
VBUS
VSS
VIO1
VSS
VIO1
VSS
VIO2
VSS
VIO3
VSS
VIO4
VSS
CVDDQ
NC
NC
VIO5
VSS
AVDD
AVSS
VDD
VSS
VDD
VSS
VDD
VDD
VDD
VDD
VDD
VSS
VSS
VSS
VSS
VSS
C8 VBUS/ I/O
VBATT
B3
R_usb2
NC
Description
Precision Resistors
Precision resistor for USB 2.0 (Connect a 6.04 k+/-1% resistor between this pin and GND)
Precision resistor for USB 3.0 (Connect a 200 +/-1% resistor between this pin and GND)
Document Number: 001-87710 Rev. *B
Page 11 of 27
11 Page | ||
| Páginas | Total 27 Páginas | |
| PDF Descargar | [ Datasheet CYUSB2025.PDF ] | |
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