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PDF CYUSB3031 Data sheet ( Hoja de datos )
| Número de pieza | CYUSB3031 | |
| Descripción | FX3S SuperSpeed USB Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYUSB303X
EZ-USB® FX3S SuperSpeed USB Controller
EZ-USB® FX3S SuperSpeed USB Controller
Features
■ Universal serial bus (USB) integration
❐ USB 3.0 and USB 2.0 peripherals compliant with USB 3.0
specification 1.0
❐ 5-Gbps USB 3.0 PHY compliant with PIPE 3.0
❐ High-speed On-The-Go (HS-OTG) host and peripheral
compliant with OTG Supplement Version 2.0
❐ Thirty-two physical endpoints
❐ Support for battery charging Spec 1.1 and accessory charger
adaptor (ACA) detection
■ General Programmable Interface (GPIF™ II)
❐ Programmable 100-MHz GPIF II enables connectivity to a
wide range of external devices
❐ 8- and 16-bit data bus
❐ As many as 16 configurable control signals
■ Mass storage support
❐ SD 3.0 (SDXC) UHS-1
❐ eMMC 4.41
❐ Two ports that can support memory card sizes up to 2TB
❐ Built-in RAID with support for RAID0 and RAID1
■ System I/O expansion with two secure digital I/O (SDIO 3.0)
ports
■ Support for USB-attached storage (UAS), mass-storage class
(MSC), human interface device (HID), full, and Turbo-MTP™
■ Fully accessible 32-bit CPU
❐ ARM926EJ core with 200-MHz operation
❐ 512-KB or 256-KB embedded SRAM
■ Additional connectivity to the following peripherals
❐ I2C master controller at 1 MHz
❐ I2S master (transmitter only) at sampling frequencies of
32 kHz, 44.1 kHz, and 48 kHz
❐ UART support of up to 4 Mbps
❐ SPI master at 33 MHz
■ Selectable clock input frequencies
❐ 19.2, 26, 38.4, and 52 MHz
❐ 19.2-MHz crystal input support
Logic Block Diagram
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on
❐ 20 µA with VBATT off
■ Independent power domains for core and I/O
❐ Core operation at 1.2 V
❐ I2S, UART, and SPI operation at 1.8 to 3.3 V
❐ I2C operation at 1.2 V
■ 10-mm × 10-mm, 0.8-mm pitch Pb-free ball grid array (BGA)
package
■ EZ-USB® software and development kit (DVK) for easy code
development
Applications
■ Digital video camcorders
■ Digital still cameras
■ Printers
■ Scanners
■ Video capture cards
■ Test and measurement equipment
■ Surveillance cameras
■ Personal navigation devices
■ Medical imaging devices
■ Video IP phones
■ Portable media players
■ Industrial cameras
■ RAID controller
■ USB Disk on Module
Functional Description
For a complete list of related resources, click here.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-84160 Rev. *F
• San Jose, CA 95134-1709 • 408-943-2600
Revised January 14, 2016
1 page  
Figure 2. EZ-USB FX3S as Main Processor
CYUSB303X
USB Interface
FX3S complies with the following specifications and supports the
following features:
■ Supports USB peripheral functionality compliant with the
USB 3.0 Specification Revision 1.0 and is also backward
compatible with the USB 2.0 Specification.
■ Complies with OTG Supplement Revision 2.0. It supports
High-Speed, Full-Speed, and Low-Speed OTG dual-role device
capability. As a peripheral, FX3S is capable of SuperSpeed,
High-Speed, and Full-Speed. As a host, it is capable of
High-Speed, Full-Speed, and Low-Speed.
■ Supports Carkit Pass-Through UART functionality on USB
D+/D– lines based on the CEA-936A specification.
■ Supports up to 16 IN and 16 OUT endpoints.
■ Supports the USB 3.0 Streams feature. It also supports USB
Attached SCSI (UAS) device-class to optimize mass-storage
access performance.
■ As a USB peripheral, FX3S supports UAS, USB Video Class
(UVC), Mass Storage Class (MSC), and Media Transfer
Protocol (MTP) USB peripheral classes. As a USB peripheral,
all other device classes are supported only in the pass-through
mode when handled entirely by a host processor external to
the device.
■ As an OTG host, FX3S supports MSC and HID device classes.
Note When the USB port is not in use, disable the PHY and
transceiver to save power.
Figure 3. USB Interface Signals
EZ-USB FX3S
VBATT
VBUS
OTG_ID
SSRX-
SSRX+
SSTX-
SSTX+
D-
D+
OTG
FX3S is compliant with the OTG Specification Revision 2.0. In
the OTG mode, FX3S supports both A and B device modes and
supports Control, Interrupt, Bulk, and Isochronous data
transfers.
FX3S requires an external charge pump (either standalone or
integrated into a PMIC) to power VBUS in the OTG A-device
mode.
The Target Peripheral List for OTG host implementation consists
of MSC- and HID-class devices.
FX3S does not support Attach Detection Protocol (ADP).
Document Number: 001-84160 Rev. *F
Page 5 of 54
5 Page 
CYUSB303X
JTAG Interface
FX3S’s JTAG interface has a standard five-pin interface to
connect to a JTAG debugger in order to debug firmware through
the CPU-core’s on-chip-debug circuitry.
Industry-standard debugging tools for the ARM926EJ-S core
can be used for the FX3S application development.
Other Interfaces
FX3S supports the following serial peripherals:
■ UART
■ I2C
■ I2S
■ SPI
The SPI, UART, and I2S interfaces are multiplexed on the serial
peripheral port.
UART Interface
The UART interface of FX3S supports full-duplex
communication. It includes the signals noted in Table 1.
Table 1. UART Interface Signals
Signal
TX
RX
CTS
RTS
Description
Output signal
Input signal
Flow control
Flow control
The UART is capable of generating a range of baud rates, from
300 bps to 4608 Kbps, selectable by the firmware. If flow control
is enabled, then FX3S's UART only transmits data when the CTS
input is asserted. In addition to this, FX3S's UART asserts the
RTS output signal, when it is ready to receive data.
I2C Interface
FX3S’s I2C interface is compatible with the I2C Bus Specification
Revision 3. This I2C interface is capable of operating only as I2C
master; therefore, it may be used to communicate with other I2C
slave devices. For example, FX3S may boot from an EEPROM
connected to the I2C interface, as a selectable boot option.
FX3S’s I2C Master Controller also supports multi-master mode
functionality.
The power supply for the I2C interface is VIO5, which is a
separate power domain from the other serial peripherals. This
gives the I2C interface the flexibility to operate at a different
voltage than the other serial interfaces.
The I2C controller supports bus frequencies of 100 kHz,
400 kHz, and 1 MHz. When VIO5 is 1.2 V, the maximum
operating frequency supported is 100 kHz. When VIO5 is 1.8 V,
2.5 V, or 3.3 V, the operating frequencies supported are 400 kHz
and 1 MHz. The I2C controller supports the clock-stretching
feature to enable slower devices to exercise flow control.
The I2C interface’s SCL and SDA signals require external pull-up
resistors. The pull-up resistors must be connected to VIO5.
I2S Interface
FX3S has an I2S port to support external audio codec devices.
FX3S functions as I2S Master as transmitter only. The I2S
interface consists of four signals: clock line (I2S_CLK), serial
data line (I2S_SD), word select line (I2S_WS), and master
system clock (I2S_MCLK). FX3S can generate the system clock
as an output on I2S_MCLK or accept an external system clock
input on I2S_MCLK.
The sampling frequencies supported by the I2S interface are
32 kHz, 44.1 kHz, and 48 kHz.
SPI Interface
FX3S supports an SPI Master interface on the Serial Peripherals
port. The maximum operation frequency is 33 MHz.
The SPI controller supports four modes of SPI communication
(see SPI Timing Specification on page 47 for details on the
modes) with the Start-Stop clock. This controller is a
single-master controller with a single automated SSN control. It
supports transaction sizes ranging from 4 bits to 32 bits.
Document Number: 001-84160 Rev. *F
Page 11 of 54
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CYUSB3031.PDF ] | |
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