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PDF CY7C68321C Data sheet ( Hoja de datos )
| Número de pieza | CY7C68321C | |
| Descripción | USB 2.0 to ATA/ATAPI Bridge | |
| Fabricantes | Cypress Semiconductor | |
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CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
EZ-USB AT2LP™ USB 2.0 to
ATA/ATAPI Bridge
EZ-USB AT2LP™ USB 2.0 to ATA/ATAPI Bridge
Features
■ Fixed Function Mass Storage Device - Requires no Firmware
■ Two Power Modes: Self Powered and USB Bus Powered to
enable Bus Powered CF (CompactFlash) Readers and Truly
Portable USB Hard Drives
■ Certified Compliant for USB 2.0 (TID# 40490119), the USB
Mass Storage Class, and the USB Mass Storage Class
Bulk-Only Transport (BOT) Specification
■ Operates at High-Speed (480 Mbps) or Full-Speed (12 Mbps)
USB
■ Complies with ATA/ATAPI-6 Specification
■ Supports 48-bit Addressing for Large Hard Drives
■ Supports ATA Security Features
■ Supports any ATA Command with the ATACB Function
■ Supports Mode for BIOS Boot Support
■ Supports ATAPI Serial Number VPD Page Retrieval for Digital
Rights Management (DRM) Compatibility
■ Supports PIO Modes 0, 3, and 4, Multiword DMA Mode 2, and
UDMA Modes 2, 3, and 4
■ Uses One Small External Serial EEPROM for Storage of USB
Descriptors and Device Configuration Data
■ ATA Interface IRQ Signal Support
■ Supports one or two ATA/ATAPI Devices
■ Supports CompactFlash and one ATA/ATAPI Device
■ Supports Board-level Manufacturing Test using the USB I/F
■ Places the ATA Interface in High Impedance (High Z) to enable
Sharing of the ATA Bus with another Controller such as an
IEEE-1394 to ATA Bridge Chip or MP3 Decoder)
■ Low Power 3.3 V Operation
■ Fully Compatible with Native USB Mass Storage Class Drivers
■ Cypress Mass Storage Class Drivers available for Windows®
(98SE, ME, 2000, XP) and Mac OS X operating systems
Features (CY7C68320C/CY7C68321C only)
■ Supports HID Interface or Custom GPIOs to enable features
such as Single Button Backup, Power Off, and LED-based
Notification
■ 56-pin QFN and 100-pin TQFP Pb-free Packages
■ CY7C68321C is Ideal for Battery Powered Designs
■ CY7C68320C is Ideal for Self and Bus Powered Designs
■ Automotive AEC Grade Option (–40 °C to 85 °C)
Features (CY7C68300C/CY7C68301C only)
■ Pin Compatible with CY7C68300A (using Backward
Compatibility Mode)
■ 56-pin SSOP and 56-pin QFN Pb-free Packages
■ CY7C68301C is Ideal for Battery Powered Designs
■ CY7C68300C is Ideal for Self and Bus Powered Designs
Errata: For information on silicon errata, see “Errata” on page 43. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-05809 Rev. *O
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 2, 2014
1 page  
CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Pin Diagrams
The AT2LP is available in different package types to meet a variety of design needs. The CY7C68320C/321C is available in 56-pin
QFN and 100-pin TQFP packages to provide the greatest flexibility for new designs. The CY7C68300C is available in 56-pin SSOP
and QFN package types and CY7C68301C is available in QFN package to ensure backward compatibility with CY7C68300A
designs.
Figure 2. 56-pin SSOP Pinout (CY7C68300C only)
1 DD13
2 DD14
3 DD15
4 GND
5 ATAPUEN (GND)
6 VCC
7 GND
8 IORDY
9 DMARQ
10 AVCC
11 XTALOUT
12 XTALIN
13 AGND
14 VCC
15 DPLUS
16 DMINUS
17 GND
18 VCC
19 GND
20 PWR500 # ( PU 10K)
21 GND(Reserved )
22 SCL
23 SDA
24 VCC
25 DD0
26 DD1
27 DD2
28 DD3
DD12
DD11
DD10
DD9
DD8
( ATA_EN ) VBUS_ ATA_ENABLE
VCC
RESET#
GND
ARESET#
( VBUS_ PWR_ VALID ) DA2
CS1#
CS0#
(DA2 ) DRVPWRVLD
DA1
DA0
INTRQ
VCC
DMACK #
DIOR #
DIOW #
GND
VCC
GND
DD7
DD6
DD5
DD4
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
Note Labels in italics denote pin functionality during CY7C68300A compatibility mode.
Document Number: 001-05809 Rev. *O
Page 5 of 46
5 Page 
CY7C68300C/CY7C68301C
CY7C68320C/CY7C68321C
Table 1. AT2LP Pin Descriptions (continued)
Note Italic pin names denote pin functionality during CY7C68300A compatibility mode
100 56 56
TQFP QFN SSOP
67 33 40
68 34 41
Pin Name
INTRQ
DA0
69 35 42
70[8] 36[8] 43
DA1
DRVPWRVLD
(DA2)
Pin Default State
Type at Startup
Pin Description
I[7] Input ATA interrupt request.
O/Z[7] Driven HIGH ATA address.
after 2 ms
delay
O/Z[7] Driven HIGH ATA address.
after 2 ms
delay
I Input Device presence detect. (See DRVPWRVLD on page 14).
Configurable logical polarity is controlled by EEPROM address
0x08. This pin must be pulled HIGH if functionality is not used.
Alternate function. Input when the EEPROM configuration
byte 8 has bit 7 set to ‘1’. The input value is reported through
EP1IN (byte 0, bit 0).
71 37 44
CS0#
O/Z[7] Driven HIGH ATA chip select.
after 2 ms
delay
72 38 45
CS1#
O/Z[7] Driven HIGH ATA chip select.
after 2 ms
delay
73 39 46
DA2
O/Z[7] Driven HIGH ATA address.
(VBUS_PWR_VALID)
after 2 ms
delay
74 40 47
ARESET#
O/Z[7]
ATA reset.
75 41 48
GND
GND
Ground.
76 N/A N/A
NC
NC
No connect.
77 42 49
RESET#
I Input Chip reset (See RESET# on page 15).
78 43 50
VCC
PWR
79 44 51 VBUS_ATA_ENABLE I
(ATA_EN)
80 45 52
DD8
I/O[7]
81 46 53
DD9
I/O[7]
82 47 54
DD10
I/O[7]
83 48 55
DD11
I/O[7]
Input
VCC. Connect to 3.3 V power source.
VBUS detection (See VBUS_ATA_ENABLE on page 15).
High Z
High Z
High Z
High Z
ATA data bit 8.
ATA data bit 9.
ATA data bit 10.
ATA data bit 11.
84 N/A N/A
GND
Ground.
85 N/A N/A
86 N/A N/A
87
88 36[8] N/A
89 13[8]
90 54[8]
91
92
93
VCC
NC
GPIO0
GPIO1
GPIO2
GPIO3
GPIO4
GPIO5
PWR
NC
I/O[8]
VCC. Connect to 3.3 V power source.
No connect.
General Purpose I/O pins (See GPIO Pins on page 14). The
GPIO pins must be tied to GND if functionality is not used.
94 N/A N/A
GND
GND
Ground.
Notes
7. If byte 8, bit 4 of the EEPROM is set to ‘0’, the ATA interface pins are only active when VBUS_ATA_EN is asserted. See VBUS_ATA_ENABLE on page 15.
8. The General Purpose inputs can be enabled on ATAPUEN, PWR500#, and DRVPWRVLD via EEPROM byte 8, bit 7 on CY7C68320C/CY7C68321C.
Document Number: 001-05809 Rev. *O
Page 11 of 46
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C68321C.PDF ] | |
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