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CY7C64713 の電気的特性と機能

CY7C64713のメーカーはCypress Semiconductorです、この部品の機能は「Full Speed USB Peripheral Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY7C64713
部品説明 Full Speed USB Peripheral Controller
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY7C64713 Datasheet, CY7C64713 PDF,ピン配置, 機能
CY7C64713
EZ-USB FX1™ USB Microcontroller
Full Speed USB Peripheral Controller
EZ-USB FX1™ USB Microcontroller Full Speed USB Peripheral Controller
Features
Single chip integrated USB transceiver, SIE, and enhanced
8051 microprocessor
Fit, form, and function upgradable to the FX2LP (CY7C68013A)
Pin compatible
Object code compatible
Functionally compatible (FX1 functionality is a subset of the
FX2LP)
Draws no more than 65 mA in any mode, making the FX1
suitable for bus powered applications
Software: 8051 runs from internal RAM, which is:
Downloaded using USB
Loaded from EEPROM
External memory device (128 pin configuration only)
16 KB of on-chip code/data RAM
Four programmable BULK/INTERRUPT/ISOCHRONOUS
endpoints
Buffering options: double, triple, and quad
Additional programmable (BULK/INTERRUPT)
endpoint
64-byte
8- or 16-bit external data interface
Smart media standard ECC generation
GPIF
Allows direct connection to most parallel interfaces; 8- and
16-bit
Programmable waveform descriptors and configuration
registers to define waveforms
Supports multiple ready (RDY) inputs and Control (CTL)
outputs
Integrated, industry standard 8051 with enhanced features:
Up to 48 MHz clock rate
Four clocks for each instruction cycle
Two USARTS
Three counters or timers
Expanded interrupt system
Two data pointers
3.3 V operation with 5 V tolerant inputs
Smart SIE
Vectored USB interrupts
Separate data buffers for the setup and DATA portions of a
CONTROL transfer
Integrated I2C controller, running at 100 or 400 KHz
48 MHz, 24 MHz, or 12 MHz 8051 operation
Four integrated FIFOs
Brings glue and FIFOs inside for lower system cost
Automatic conversion to and from 16-bit buses
Master or slave operation
FIFOs can use externally supplied clock or asynchronous
strobes
Easy interface to ASIC and DSP ICs
Vectored for FIFO and GPIF Interrupts
Up to 40 general purpose IOs (GPIO)
Four package options:
128-pin TQFP
100-pin TQFP
56-pin SSOP
56-pin QFN Pb-free
Errata: For information on silicon errata, see “Errata” on page 71. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 38-08039 Rev. *L
• San Jose, CA 95134-1709 • 408-943-2600
Revised March 9, 2014

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CY7C64713 pdf, ピン配列
CY7C64713
Contents
Functional Description ..................................................... 4
Applications ...................................................................... 4
Functional Overview ........................................................ 4
USB Signaling Speed .................................................. 4
8051 Microprocessor ................................................... 4
I2C Bus ........................................................................ 5
Buses .......................................................................... 5
USB Boot Methods ...................................................... 5
ReNumeration™ .......................................................... 6
Bus-powered Applications ........................................... 6
Interrupt System .......................................................... 6
Reset and Wakeup ...................................................... 8
Program/Data RAM ..................................................... 9
Endpoint RAM ........................................................... 11
External FIFO Interface ............................................. 11
GPIF .......................................................................... 12
ECC Generation ........................................................ 13
USB Uploads and Downloads ................................... 13
Autopointer Access ................................................... 13
I2C Controller ............................................................. 13
Compatible with Previous Generation
EZ-USB FX2 ..................................................................... 14
Pin Assignments ............................................................ 14
CY7C64713 Pin Definitions ............................................ 20
Register Summary .......................................................... 28
Absolute Maximum Ratings .......................................... 47
Operating Conditions ..................................................... 47
DC Characteristics ......................................................... 47
USB Transceiver ....................................................... 47
AC Electrical Characteristics ........................................ 48
USB Transceiver ....................................................... 48
PORTC Strobe Feature Timings ............................... 51
GPIF Synchronous Signals ....................................... 52
Slave FIFO Synchronous Read ................................. 53
Slave FIFO Asynchronous Read ............................... 54
Slave FIFO Synchronous Write ................................. 55
Slave FIFO Asynchronous Write ............................... 56
Slave FIFO Synchronous Packet End Strobe ........... 56
Slave FIFO Asynchronous Packet End Strobe ......... 58
Slave FIFO Output Enable ........................................ 58
Slave FIFO Address to Flags/Data ............................ 58
Slave FIFO Synchronous Address ............................ 59
Slave FIFO Asynchronous Address .......................... 59
Sequence Diagram .................................................... 60
Ordering Information ...................................................... 64
Ordering Code Definitions ......................................... 64
Package Diagrams .......................................................... 65
Quad Flat Package No Leads (QFN) Package
Design Notes ................................................................... 68
Acronyms ........................................................................ 70
Document Conventions ................................................. 70
Units of Measure ....................................................... 70
Errata ............................................................................... 71
Part Numbers Affected .............................................. 71
EZ-USB FX1 Qualification Status .............................. 71
EZ-USB FX1 Errata Summary .................................. 71
Document History Page ................................................. 72
Sales, Solutions, and Legal Information ...................... 74
Worldwide Sales and Design Support ....................... 74
Products .................................................................... 74
PSoC® Solutions ...................................................... 74
Cypress Developer Community ................................. 74
Technical Support ..................................................... 74
Document Number: 38-08039 Rev. *L
Page 3 of 74


3Pages


CY7C64713 電子部品, 半導体
CY7C64713
ReNumeration™
Because the FX1’s configuration is soft, one chip can take on the
identities of multiple distinct USB devices.
When first plugged into the USB, the FX1 enumerates
automatically and downloads firmware and the USB descriptor
tables over the USB cable. Next, the FX1 enumerates again, this
time as a device defined by the downloaded information. This
patented two step process, called ReNumeration, happens
instantly when the device is plugged in, with no indication that
the initial download step has occurred.
Two control bits in the USBCS (USB Control and Status) register
control the ReNumeration process: DISCON and RENUM. To
simulate a USB disconnect, the firmware sets DISCON to 1. To
reconnect, the firmware clears DISCON to 0.
Before reconnecting, the firmware sets or clears the RENUM bit
to indicate if the firmware or the Default USB Device handles
device requests over endpoint zero:
RENUM = 0, the Default USB Device handles device requests
RENUM = 1, the firmware handles device requests
Bus-powered Applications
The FX1 fully supports bus powered designs by enumerating
with less than 100 mA as required by the USB specification.
Interrupt System
INT2 Interrupt Request and Enable Registers
FX1 implements an autovector feature for INT2 and INT4. There
are 27 INT2 (USB) vectors, and 14 INT4 (FIFO/GPIF) vectors.
See EZ-USB Technical Reference Manual (TRM) for more
details.
USB-Interrupt Autovectors
The main USB interrupt is shared by 27 interrupt sources. The
FX1 provides a second level of interrupt vectoring, called
Autovectoring, to save code and processing time that is normally
required to identify the individual USB interrupt source. When a
USB interrupt is asserted, the FX1 pushes the program counter
on to its stack and then jumps to address 0x0043, where it
expects to find a “jump” instruction to the USB Interrupt service
routine.
The FX1 jump instruction is encoded as shown in Table 3.
If Autovectoring is enabled (AV2EN = 1 in the INTSETUP
register), the FX1 substitutes its INT2VEC byte. Therefore, if the
high byte (“page”) of a jump table address is preloaded at
location 0x0044, the automatically inserted INT2VEC byte at
0x0045 directs the jump to the correct address out of the 27
addresses within the page.
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual
USB-interrupt sources, the FIFO/GPIF interrupt is shared among
14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, such
as the USB Interrupt, can employ autovectoring. Table 4 on page
7 shows the priority and INT4VEC values for the 14 FIFO/GPIF
interrupt sources.
FIFO/GPIF Interrupt (INT4)
Just as the USB Interrupt is shared among 27 individual
USB-interrupt sources, the FIFO/GPIF interrupt is shared among
14 individual FIFO/GPIF sources. The FIFO/GPIF Interrupt, such
as the USB Interrupt, can employ autovectoring.
Table 4 on page 7 shows the priority and INT4VEC values for the
14 FIFO/GPIF interrupt sources.
Table 3. INT2 USB Interrupts
Priority
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
USB INTERRUPT TABLE FOR INT2
INT2VEC Value
Source
Notes
00 SUDAV
Setup Data Available
04 SOF
Start of Frame
08 SUTOK
Setup Token Received
0C SUSPEND
USB Suspend request
10 USB RESET
Bus reset
14 Reserved
18 EP0ACK
FX1 ACK’d the CONTROL Handshake
1C Reserved
20 EP0-IN
EP0-IN ready to be loaded with data
24 EP0-OUT
EP0-OUT has USB data
28 EP1-IN
EP1-IN ready to be loaded with data
2C EP1-OUT
EP1-OUT has USB data
30 EP2
IN: buffer available. OUT: buffer has data
34 EP4
IN: buffer available. OUT: buffer has data
38 EP6
IN: buffer available. OUT: buffer has data
3C EP8
IN: buffer available. OUT: buffer has data
40 IBN
IN-Bulk-NAK (any IN endpoint)
Document Number: 38-08039 Rev. *L
Page 6 of 74

6 Page



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部品番号部品説明メーカ
CY7C64713

Full Speed USB Peripheral Controller

Cypress Semiconductor
Cypress Semiconductor


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