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PDF CYWB0321ABX-FDXI Data sheet ( Hoja de datos )
| Número de pieza | CYWB0321ABX-FDXI | |
| Descripción | Arroyo USB and Mass Storage Peripheral Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
West Bridge®: Arroyo USB and
Mass Storage Peripheral Controller
West Bridge®: Arroyo USB and Mass Storage Peripheral Controller
Features
■ Multimedia device support
❐ Support next-gen SD, SDHC, SDIO, and MMC+
■ Simultaneous link to independent multimedia (SLIM®)
architecture, enabling simultaneous and independent data
paths between the processor and USB, and between the USB
and mass storage.
■ High speed USB at 480 Mbps
❐ USB 2.0 compliant
❐ Integrated USB 2.0 transceiver, smart Serial Interface Engine
❐ 16 programmable endpoints
■ Flexible processor interface, which supports:
❐ SPI (slave mode) interface
❐ Multiplexing and nonmultiplexing address and data interface
❐ SRAM interface
❐ Pseudo CRAM interface
❐ Pseudo NAND Flash interface
❐ DMA slave support
Logic Block Diagram
■ Ultra low power, 1.8 V core operation
■ Low power modes
■ Small footprint, 3.9 × 3.9 mm, 0.4 mm pitch, WLCSP
■ Supports USB Boot, I2C Boot and Processor Boot
■ Clock input frequency
❐ 19.2 MHz
❐ 26 MHz
Applications
■ Cellular phones
■ Portable media players
■ Personal digital assistants
■ Portable navigation devices
■ Digital cameras
■ POS terminals
■ Portable video recorders
Control Registers
µC
Access Control
P
SLIM™
Mass Storage Interface
SD/MMC
S
U
Errata: For information on silicon errata, see “Errata” on page 50 and “Errata” on page 51. Details include trigger conditions, devices affected, and proposed workaround.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-57458 Rev. *H
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 1, 2014
1 page  
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
UVDDQ: This is the 3.3 V nominal supply for the USB I/O and
some analog circuits. It also supplies power to the USB
transceiver.
VDD: This is the supply voltage for the logic core. The nominal
supply voltage level is 1.8 V. This supplies the core logic circuits.
The same supply must also be used for AVDDQ.
AVDDQ: This is the 1.8 V supply for PLL and USB serializer
analog components. The same supply must also be used for
VDD. Maximum permitted noise on AVDDQ is 20 mV p-p.
XVDDQ: This is the clock I/O supply; 3.3 V for XTAL or 1.8 V for
an external clock.
Noise guideline for all supplies except AVDDQ is maximum
100 mV p-p. All I/O supplies of Arroyo must be ON when a
system is active even if Arroyo is not in use. The core VDD can
also be deactivated at any time to preserve power, provided
there is a minimum impedance of 1 k between the VDD pin and
ground. All I/Os tristate when the core is disabled.
Figure 2. Arroyo Power Supply Domains
*VDDQ
VDD
UVDDQ
I/O D-CORE
USB-IO
D+
D-
Power Supply Sequence
The power supplies are independently sequenced without
damaging the part. All power supplies must be up and stable
before the device operates. If the supplies are not stable, the
remaining domains are in low power (standby) state.
Power Modes
In addition to the normal operating mode, Arroyo contains
several low power states when normal operation is not required.
Normal Mode
Normal mode is the mode in which Arroyo is fully functional. In
this mode data transfer functions described in this document are
performed.
Suspend Mode
This mode is entered internally by 8051 (external processor only
initiates entry into this mode through Mailbox commands). This
mode is exited by the D+ bus going low, GPIO[0] going to a
pre-determined state or by asserting CE# LOW.
In Arroyo’s suspend mode:
■ The clocks are shut off.
■ All I/Os maintain their previous state.
■ Core power supply must be retained.
■ The states of the configuration registers, endpoint buffers, and
the program RAM are maintained. All transactions must be
complete before Arroyo enters suspend mode (state of
outstanding transactions are not preserved).
■ The firmware resumes its operation from where it was
suspended, since the program counter is not reset.
■ Only inputs that are sensed are RESET#, GPIO[0]/SD_CD,
GPIO[1], SD_D3, D+, and CE#. The last three are wake up
sources (each can be individually enabled or disabled).
■ Hard Reset can be performed by asserting the RESET# input,
and Arroyo is initialized.
Standby Mode
Standby mode is a low power state. This is the lowest power
mode of Arroyo while still maintaining external supply levels. This
mode is entered through deassertion of the WAKEUP input pin
or through internal register settings. To leave this mode, assert
WAKEUP, CE#, and RESET#; and change the state of
GPIO[0]/SD_CD, GPIO[1], or SD_D3.
In this mode all configuration register settings and program RAM
contents are preserved. However, data in the buffers or other
parts of the data path, if any, is not guaranteed in values.
Therefore, the external processor must ensure that the required
data is read before putting Arroyo into the standby mode.
In the standby mode:
■ The program counter is reset on waking up from standby mode.
■ All outputs are tristated and I/O is placed in input only
configuration. Values of I/Os in standby mode are listed in the
pin assignments table.
■ Core power supply must be retained.
■ Hard Reset can be performed by asserting the RESET# input,
and Arroyo is initialized.
■ PLL is disabled.
Core Power Down Mode
The core power supply VDD is powered down in this state.
AVDDQ is tied to the same supply as VDD and is hence, also
powered down. Neither the endpoint buffers, configuration
registers nor program RAM maintain state. It is required that all
VDDQ power supplies (except AVDDQ) are on and not power
downer down in this mode. When UVDDQ is powered down,
D+/D– can’t be driven by external device.
The core power down mode has two power down options:
■ Core only power down – VDD power down.
■ Core and USB power down – VDD and UVDDQ are both
powered down.
In these power down options, the endpoint buffers, configuration
registers, or the program RAM do not maintain state. It is
necessary to reload the firmware on exiting from this mode. It is
required that all VDDQ power supplies are on and not powered
down in this mode.
Document Number: 001-57458 Rev. *H
Page 5 of 54
5 Page 
CYWB0320ABX-FDXI
CYWB0321ABX-FDXI
Figure 3. CYWB0320ABX-FDXI WLCSP Ball Map - Top View
123456789
A SD_CMD SD_D[6] SD_CLK SD_D[2] SD_D[0] GPIO[0] INT# TEST[0] XTALOUT A
B NAND_IO[1] NAND_IO[0] SD_D[5] SD_D[3] SD_D[1] GVDDQ RESET# AVSSQ XTALIN
B
C NAND_IO[4] NAND_IO[3] VGND SD_D[7] SD_D[4] DACK# TEST[2] AVDDQ UVSSQ
C
D
NAND_IO[6] NAND_IO[5] NAND_IO[2] VGND
SSVDDQ
DRQ#
NC XVDDQ D+
D
E NAND_IO[7] A[7]
VGND
VDD
WAKEUP TEST[1]
NC UVDDQ
D-
E
F
SCAN
A[5]
DQ[15]
PVDDQ
VGND
DQ[5]
VDD
OE#
VDD
F
G
TESTTREE
A[4]
VGND
DQ[12]
VDD
DQ[8]
DQ[2]
ADV#
WE#
G
H
A[6]
A[2]
A[0]
DQ[13]
DQ[10]
DQ[7]
DQ[3]
DQ[1]
DQ[0]
H
J
A[3]
A[1]
CE#
DQ[14]
DQ[11]
DQ[9]
DQ[6]
DQ[4]
PVDDQ
J
123456789
POWER DOMAIN KEY
UVDDQ
UVSSQ
GVDDQ
SSVDDQ
VDD/AVDDQ
VGND/AVSSQ
PVDDQ
XVDDQ
Document Number: 001-57458 Rev. *H
Page 11 of 54
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| PDF Descargar | [ Datasheet CYWB0321ABX-FDXI.PDF ] | |
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