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PDF CYWB0163BB Data sheet ( Hoja de datos )
| Número de pieza | CYWB0163BB | |
| Descripción | USB and Mass Storage Controller | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CYWB0163BB/CYWB0164BB
West Bridge® Bay™ USB and Mass
Storage Controller
Features
■ Best-in-class sideloading performance (>30 MBps) based on
Cypress's proprietary SLIM® II technology, enabling direct path
from Hi-Speed USB 2.0 to mass storage devices
■ USB-IF compliance certified
❐ USB 2.0 peripheral
❐ High-Speed On-The-Go (HS-OTG) 2.0 host negotiation pro-
tocol (HNP) and session request protocol (SRP)
❐ Thirty-two endpoints
❐ Integrated USB 2.0 transceivers
❐ EZ-Dtect™ – USB charger detection 1.1
❐ Accessory charger adaptor (ACA)
❐ Integrated Hi-Speed USB 2.0 switch[1]
❐ Carkit Pass-Through UART functionality on USB
■ Mass storage support
❐ SD 3.0 (SDXC) UHS-1
❐ eMMC 4.4
■ System I/O expansion with two secure digital I/O (SDIO) ports
■ Native mass storage class (MSC), human interface device
(HID), full, and Turbo-MTPTM support
■ Flexible host processor interface
❐ Asynchronous non-multiplexed SRAM
❐ Synchronous and asynchronous address/data multiplexed
SRAM
❐ Multimedia card (MMC) slave with eMMC 4.3/4.4
pass-through boot
❐ Direct memory access (DMA) slave support over processor
interfaces
■ Ultra low-power in core power-down mode
❐ Less than 60 µA with VBATT on and 20 µA with VBATT off
■ Independent and flexible power domains
■ Flexible serial peripheral interfaces (SPIs)
❐ I2C master controller at 1 MHz
❐ I2S master (transmitter only) with sampling frequencies of
32 kHz, 44.1 kHz, and 48 kHz
❐ UART at 4 Mbps
❐ SPI master at 33 MHz
■ Selectable clocking frequencies
❐ 19.2-, 26-, 38.4-, and 52-MHz clock input
❐ 19.2-MHz crystal input
❐ 32-kHz low-power clock for watchdog timer
■ Package options:
❐ 5.099 mm × 4.695 mm × 0.55 mm, with 0.4 mm pitch small
footprint wafer-level chip scale package (WLCSP)
❐ 10 × 10 mm, 0.8-mm pitch ball grid array (BGA) package
■ Pin compatible with West Bridge® Benicia™ enabling easy
migration to USB 3.0
Applications
■ Mobile phones
■ Portable media players
■ Portable navigation devices
■ Personal digital assistant devices
■ Digital still/video cameras
Note
1. Available only with the WLCSP package.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-45550 Rev. *J
• San Jose, CA 95134-1709 • 408-943-2600
Revised April 21, 2014
1 page  
CYWB0163BB/CYWB0164BB
Figure 2. Carkit UART Pass-Through Block Diagram
Carkit UART pass through
interface on P-Port.
UART_TXD
UART_RXD
S2_GPIO[48]
Carkit UART pass through (LPP_UART_TX)
interface on S2-Port.
S2_GPIO[49]
(LPP_UART_RX)
Carkit UART Pass Through
TXD
RXD
DP
USB PHY DM
RXD (DP)
TXD (DM)
EZ-Dtect
Bay supports USB the charger and accessory detection
mechanism (EZ-Dtect). The charger detection mechanism
complies with the battery-charging specification, revision 1.1.
Bay also provides hardware support to detect the resistance
values on the ID pin.
The Bay device detects the following resistance ranges:
■ Less than 10
■ Less than 1 k
■ 65 k to 72 k
■ 35 kto 39 k
■ 99.96 k to 104.4 k (102 k2%)
■ 119 k to 132 k
■ Higher than 220 k
■ 431.2 k to 448.8 k (440 k2%)
Bay's EZ-Dtect feature can identify a dedicated wall charger,
host/hub charger, and host/hub.
Figure 3 shows the flowchart of the charger detection procedure
that Bay uses. Table 1 on page 7 shows the messages that Bay
may communicate over I2C to an external PMIC or processor.
Document Number: 001-45550 Rev. *J
Page 5 of 52
5 Page 
CYWB0163BB/CYWB0164BB
Boot Options
Bay can load boot images from various sources, selected by the
configuration of the PMODE pins. These include:
■ Boot from eMMC (S0-Port)
■ Boot from I2C
■ Boot from asynchronous ADMux (P-Port)
■ Boot from synchronous ADMux (P-Port)
■ Boot from asynchronous non-multiplexed SRAM (P-Port)
■ Boot from PMMC (P-Port)
USB boot can be enabled as a fallback boot option.
Table 3. West Bridge Bay Booting Options
PMODE[2:0]
000
001
010
011
100
101
110
111
00F[3]
01F[3]
10F[3]
11F[3]
1F1[3]
Other Combinations
Boot From
S0-Port (eMMC)
On failure, USB boot is enabled
PMMC pass- through
On failure, USB boot enabled
PMMC pass-through
PMMC_Relay (enables secure boot)
S0-Port (eMMC)
Sync ADMux (16-bit data bus)
PMMC legacy
USB Boot
Async SRAM (16-bit data bus)
Async ADMux (16-bit data bus)
I2C
On failure, USB boot is enabled
I2C only
PMMC_Relay (enables secure boot)
On failure USB boot is enabled
Reserved
Reset
Hard Reset
A hard reset is initiated by asserting the RESET# pin on West
Bridge Bay. The specific reset sequence and timing
requirements are detailed in Figure 23 on page 43 and Figure 17
on page 42. All I/Os are tristated during a hard reset.
Soft Reset
In a soft reset, the processor sets the appropriate bits in the
PP_INIT control register. There are two types of soft reset:
■ CPU Reset - The CPU Program Counter is reset. Firmware
does not need to be reloaded following a CPU Reset.
■ Whole Device Reset - This reset is identical to hard reset. The
firmware must be reloaded following a Whole Device Reset.
Clocking
Bay allows either a crystal to be connected between the XTALIN
and XTALOUT pins or an external clock to be connected at the
CLKIN pin. The XTALIN, XTALOUT, CLKIN, and CLKIN_32 pins
can be left unconnected if not used.
Crystal frequency supported is 19.2 MHz, and the external clock
frequencies supported are 19.2, 26, 38.4, and 52 MHz.
Bay has an on-chip oscillator circuit that uses an external
19.2-MHz (±100 ppm) crystal (when the crystal option is used).
An appropriate load capacitance is required with a crystal. Refer
to the specification of the crystal used to determine the
appropriate load capacitance. The FSLC[2:0] pins must be
configured appropriately to select the crystal- or clock-frequency
option. The configuration options are shown in Table 4 on page
11.
Clock inputs to Bay must meet the phase noise and jitter require-
ments specified in Table 5 on page 12.
The input clock frequency is independent of the Bay core’s
clock/data rate or any of the device interfaces (including P-Port
and S-Port). The internal PLL applies the appropriate clock
multiply option depending on the input frequency.
Table 4. Crystal/Clock Frequency Selection
FSLC[2]
0
1
1
1
1
FSLC[1]
0
0
0
1
1
FSLC[0]
0
0
1
0
1
Crystal/Clock
Frequency
19.2-MHz crystal
19.2-MHz input CLK
26-MHz input CLK
38.4-MHz input CLK
52-MHz input CLK
Note
3. F indicates Floating.
Document Number: 001-45550 Rev. *J
Page 11 of 52
11 Page | ||
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| PDF Descargar | [ Datasheet CYWB0163BB.PDF ] | |
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