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PDF CY7C65211A Data sheet ( Hoja de datos )
| Número de pieza | CY7C65211A | |
| Descripción | USB-Serial Single-Channel Bridge | |
| Fabricantes | Cypress Semiconductor | |
| Logotipo |  |
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CY7C65211
CY7C65211A
USB-Serial Single-Channel (UART/I2C/SPI)
Bridge with CapSense® and BCD
USB-Serial Single-Channel (UART/I2C/SPI) Bridge with CapSense® and BCD
Features
■ USB 2.0-certified, Full-Speed (12 Mbps)
❐ Supports communication driver class (CDC), personal health
care device class (PHDC), and vendor-device class
❐ Battery charger detection (BCD) compliant with USB Battery
Charging Specification, Rev. 1.2 (Peripheral Detect only)
❐ Integrated USB termination resistors
■ Single-channel configurable UART interface
❐ Data rates up to 3 Mbps
❐ 190 bytes for each transmit and receive buffer
❐ Supports 2-pin,4-pin and 6-pin UART interface
❐ Data format:
• 7 to 8 data bits
• 1 to 2 stop bits
• No parity, even, odd, mark, or space parity
❐ Supports parity, overrun, and framing errors
❐ Supports flow control using CTS, RTS, DTR, DSR
❐ Supports UART break signal
❐ CY7C65211 supports single channel RS232/RS422
interfaces whereas CY7C65211A supports
RS232/RS422/RS485 interfaces
■ Single-channel configurable SPI interface
❐ Data rate up to 3 MHz for SPI master and 1 MHz for SPI slave
❐ Data width: 4 bits to 16 bits
❐ 256 bytes for each transmit and receive buffer
❐ Supports Motorola, TI, and National SPI modes
■ Single-channel configurable I2C interface
❐ Master/slave up to 400 kHz
❐ 256 bytes each transmit and receive buffer
❐ Supports multi-master I2C
■ CapSense®
❐ SmartSense™ Auto-Tuning is supported through a
Cypress-supplied configuration utility
❐ Max CapSense buttons: 5
❐ GPIOs linked to CapSense buttons
■ General-purpose input/output (GPIO) pins: 10
■ Supports unique serial number feature for each device, which
fixes the COM port number permanently when USB-serial
Bridge controller as CDC device plugs in
■ 512-byte flash for storing configuration parameters
■ Configuration utility (Windows) to configure the following:
❐ Vendor ID (VID), Product ID (PID), and Product and
Manufacturer descriptors
❐ UART/I2C/SPI
USB-Compliant
❐ CapSense
❐ Charger detection
❐ GPIO
■ Driver support for VCOM and DLL
❐ Windows 10: 32- and 64-bit versions
❐ Windows 8.1: 32- and 64-bit versions
❐ Windows 8: 32- and 64-bit versions
❐ Windows 7: 32- and 64-bit versions
❐ Windows Vista: 32- and 64-bit versions
❐ Windows XP: 32- and 64-bit versions
❐ Windows CE
❐ Mac OS-X: 10.6, 10.7
❐ Linux: Kernel version 2.6.35 onwards.
❐ Android: Gingerbread and later versions
■ Clocking: Integrated 48-MHz clock oscillator
■ Supports bus-/self-powered configurations
■ USB Suspend mode for low power
■ Operating voltage: 1.71 to 5.5 V
■ Operating temperature:
❐ Commercial: 0 °C to 70 °C
❐ Industrial: –40 °C to 85 °C
■ ESD protection: 2.2-kV HBM
■ RoHS-compliant package
❐ 24-pin QFN (4.0 mm × 4.0 mm, 0.55 mm, 0.5 mm pitch)
■ Ordering part number
❐ CY7C65211-24LTXI
❐ CY7C65211A-24LTXI
Applications
■ Medical/healthcare devices
■ Point-of-Sale (POS) terminals
■ Test and measurement system
■ Gaming systems
■ Set-top box PC-USB interface
■ Industrial
■ Networking
■ Enabling USB connectivity in legacy peripherals
Functional Description
For a complete list of related resources, click here.
The USB-Serial Single-Channel Bridge with CapSense and BCD (CY7C65211/CY7C65211A) is fully
compliant with the USB 2.0 specification and Battery Charging Specification v1.2, USB-IF Test-ID (TID)
40001521.
Cypress Semiconductor Corporation • 198 Champion Court
Document Number: 001-82042 Rev. *I
• San Jose, CA 95134-1709 • 408-943-2600
Revised December 24, 2015
1 page  
CY7C65211
CY7C65211A
The DSR#/DTR# signals are used to establish a communication
link with the UART. These signals complement each other in their
functionality, similar to CTS# and RTS#.
SPI Interface
The SPI interface supports an SPI Master and SPI Slave. This
interface supports the Motorola, TI, and National Microwire
protocols. The maximum frequency of operation is 3 MHz in SPI
master mode and 1 MHz in SPI slave mode. It can support
transaction sizes ranging from 4 bits to 16 bits in length, SPI
slave supports 4 bits to 8 bits and 12 bits to 16 bits data width at
1 MHz operation. Whereas, it supports 9 bits,10 bits and 11 bits
data width operation at 500 kHz operation. (refer to USB to SPI
Bridge on page 25 for more details).
I2C Interface
The I2C interface implements full multi-master/slave modes and
supports up to 400 kHz. The configuration utility tool is used to
set the I2C address in the slave mode. The tool enables only
even slave addresses. For further details on the protocol, refer
to the NXP I2C specification, Rev. 5.
Notes
■ I2C ports are not tolerant of higher voltages. Therefore, they
cannot be hot-swapped or powered up independently when
chip is not powered.
■ The minimum fall time of the SCL is met (as per NXP I2C
specification Rev. 5) when VDDD is between 1.71 V and 3.0 V.
When VDDD is within the range of 3.0 V to 3.6 V, it is
recommended to add a 50 pF capacitor on the SCL signal.
CapSense
CapSense functionality is supported on all the GPIO pins. Any
GPIO pin can be configured as a sense pin (CS0–CS7) using the
configuration utility. When implementing CapSense functionality,
the GPIO_0 pin (configured as a modulator capacitor - Cmod)
should be connected to ground through a 2.2-nF capacitor (see
Figure 13 on page 23).
CY7C65211 supports SmartSense Auto-Tuning of the
CapSense parameters and does not require manual tuning.
SmartSense Auto-tuning compensates for printed circuit board
(PCB) variations and device process variations.
Optionally, any GPIO pin can be configured as a Cshield and
connected to the shield of the CapSense button, as shown in
Figure 13 on page 23. Shield prevents false triggering of buttons
due to water droplets and guarantees CapSense operation
(sensors respond to finger touch).
GPIOs can be linked to the CapSense buttons to indicate the
presence of a finger. CapSense functionality can be configured
using the configuration utility.
CY7C65211 supports up to five CapSense buttons. For more
information on CapSense, refer to Getting Started with
CapSense.
GPIO Interface
CY7C65211/CY7C65211A has 10 GPIOs. The maximum
available GPIOs for configuration is 10 if one two-pin (I2C/2-pin
UART) serial interface is implemented. The configuration utility
allows configuration of the GPIO pins. The configurable options
are as follows:
■ TRISTATE: GPIO tristated
■ DRIVE 1: Output static 1
■ DRIVE 0: Output static 0
■ POWER#: Power control for bus power designs
■ TXLED#: Drives LED during USB transmit
■ RXLED#: Drives LED during USB receive
■ TX or RX LED#: Drives LED during USB transmit or receive
GPIO can be configured to drive LED at 8-mA drive strength.
■ BCD0/BCD1: Two-pin output to indicate the type of USB
charger
■ BUSDETECT: Connects the VBUS pin for USB host detection
■ CS0–CS4: CapSense button input (Sense pin)
■ CSout0–CSout2: Indicates which CapSense button is pressed
■ Cmod: External modulator capacitor; connects a 2.2-nF
capacitor (±10%) to ground (GPIO_0 only)
■ Cshield: Shield for waterproofing
Memory
CY7C65211/CY7C65211A has a 512-byte flash. Flash is used
to store USB parameters, such as VID/PID, serial number,
product and manufacturer descriptors, which can be
programmed by the configuration utility.
System Resources
Power System
CY7C65211/CY7C65211A supports the USB Suspend mode to
control power usage. CY7C65211 operates in bus-powered or
self-powered modes over a range of 3.15 to 5.5 V.
Clock System
CY7C65211/CY7C65211A has a fully integrated clock with no
external components required. The clock system is responsible
for providing clocks to all subsystems.
Internal 48-MHz Oscillator
The internal 48-MHz oscillator is the primary source of internal
clocking in CY7C65211.
Internal 32-kHz Oscillator
The internal 32-kHz oscillator is primarily used to generate
clocks for peripheral operation in the USB Suspend mode.
Reset
The reset block ensures reliable power-on reset and brings the
device back to the default known state. The nXRES (active low)
pin can be used by the external devices to reset the
CY7C65211/CY7C65211A.
Suspend and Resume
The CY7C65211/CY7C65211A device asserts the SUSPEND
pin when the USB bus enters the suspend state. This helps in
meeting the stringent suspend current requirement of the USB
2.0 specification, while using the device in bus-powered mode.
The device resumes from the suspend state under either of the
two following conditions:
1. Any activity is detected on the USB bus
Document Number: 001-82042 Rev. *I
Page 5 of 34
5 Page 
SPI Specifications
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
MISO
(input)
MOSI
(output)
Figure 1. SPI Master Timing
FSPI
TDSI
LSB
TDMO
LSB
MSB
MSB
THMO
SPI Master Timing for CPHA = 0 (Refer to Table 15)
SCK
(CPOL=0,
Output)
SCK
(CPOL=1,
Output)
MISO
(input)
MOSI
(output)
FSPI
TDMO
TDSI
LSB
THMO
LSB
MSB
MSB
SPI Master Timing for CPHA = 1 (Refer to Table 15)
CY7C65211
CY7C65211A
Document Number: 001-82042 Rev. *I
Page 11 of 34
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet CY7C65211A.PDF ] | |
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