CY7C63823 Datasheet PDF - Cypress Semiconductor
| Part Number | CY7C63823 | |
| Description | Low-Speed USB Peripheral Controller | |
| Manufacturers | Cypress Semiconductor | |
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CY7C63310
CY7C638xx
enCoRe™ II
Low-Speed USB Peripheral Controller
1.0 Features
• enCoReTM II USB—“enhanced Component Reduction”
— Crystalless oscillator with support for an external clock.
The internal oscillator eliminates the need for an external
crystal or resonator
— Two internal 3.3V regulators and internal USB pull-up
resistor
www.DataSheet4U.com
— Configurable IO for real-world interface without external
components
• USB Specification Compliance
— Conforms to USB Specification, Version 2.0
— Conforms to USB HID Specification, Version 1.1
— Supports one Low-Speed USB device address
— Supports one control endpoint and two data endpoints
— Integrated USB transceiver with dedicated 3.3V
regulator for USB signalling and D- pull up.
• Enhanced 8-bit microcontroller
— Harvard architecture
— M8C CPU speed can be up to 24 MHz or sourced by an
external clock signal
• Internal memory
— Up to 256 bytes of RAM
— Up to eight Kbytes of Flash including EEROM emulation
• Interface can autoconfigure to operate as PS/2 or USB
— No external components for switching between PS/2 and
USB modes
— No GPIO pins needed to manage dual-mode capability
• Low power consumption
— Typically 10 mA at 6 MHz
— 10 µA sleep
• In-system re-programmability
— Allows easy firmware update
• General purpose I/O ports
— Up to 20 General Purpose I/O (GPIO) pins
— High current drive on GPIO pins. Configurable 8- or 50-
mA/pin current sink on designated pins
— Each GPIO port supports high-impedance inputs,
configurable pull up, open drain output, CMOS/TTL
inputs, and CMOS output
— Maskable interrupts on all I/O pins
• A dedicated 3.3V regulator for the USB PHY. Aids in
signalling and D-line pull-up
• 125 mA 3.3V voltage regulator can power external 3.3V
devices
• 3.3V I/O pins
— 4 I/O pins with 3.3V logic levels
— Each 3.3V pin supports high-impedance input, internal
pull up, open drain output or traditional CMOS output
• SPI serial communication
— Master or slave operation
— Configurable up to 4 Mbit/second transfers in the master
mode
— Supports half duplex single data line mode for optical
sensors
• 2-channel 8-bit or 1-channel 16-bit capture timer registers.
Capture timer registers store both rising and falling edge
times
— Two registers each for two input pins
— Separate registers for rising and falling edge capture
— Simplifies interface to RF inputs for wireless applications
• Internal low-power wake-up timer during suspend mode
— Periodic wake-up with no external components
• 12-bit Programmable Interval Timer with interrupts
• Advanced development tools based on Cypress
MicroSystems PSoC™ tools
• Watchdog timer (WDT)
• Low-voltage detection with user-configurable threshold
voltages
• Operating voltage from 4.0V to 5.5VDC
• Operating temperature from 0–70°C
• Available in 16/18-pin PDIP, 16/18/24-pin SOIC, 24-pin
QSOP and 32-lead QFN packages
• Industry standard programmer support
1.1 Applications
The CY7C63310/CY7C638xx is targeted for the following
applications:
• PC HID devices
— Mice (optomechanical, optical, trackball)
• Gaming
— Joysticks
— Game pad
• General-purpose
— Barcode scanners
— POS terminal
— Consumer electronics
— Toys
— Remote controls
— Security dongles
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document 38-08035 Rev. *I
Revised September 26, 2006
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CY7C63310
CY7C638xx
5.1 Pinouts Assignments
Table 5-1. Pin Assignments
32 24 24 18
QFN QSOP SOIC SIOC
18
PDIP
16
SOIC
16
PDIP
Name
Description
21 19 18
22 20 19
P3.0
P3.1
GPIO Port 3 – configured as a group (byte)
9 11 11
8 10 10
P2.0
P2.1
GPIO Port 2 – configured as a group (byte)
www.DataSheet4U1.c4om 14 13 10 15 9 13 P1.0/D+ GPIO Port 1 bit 0/USB D+[1] If this pin is used as a
General Purpose output, it will draw current. This pin
must be configured as an input to reduce current
draw.
15 15 14 11 16 10 14 P1.1/D– GPIO Port 1 bit 1/USB D–[1] If this pin is used as a
General Purpose output, it will draw current. This pin
must be configured as an input to reduce current
draw.
18 17 16 13 18 12 16 P1.2/VREG GPIO Port 1 bit 2—Configured individually.
3.3V if regulator is enabled. (The 3.3V regulator is not
available in the CY7C63310 and CY7C63801.) A 1-µF
min, 2-µF max capacitor is required on Vreg output.
20 18 17 14 1 13 1 P1.3/SSEL GPIO Port 1 bit 3—Configured individually.
Alternate function is SSEL signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
23 21 20 15 2 14 2 P1.4/SCLK GPIO Port 1 bit 4—Configured individually.
Alternate function is SCLK signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
24 22 21 16 3 15 3 P1.5/SMOSI GPIO Port 1 bit 5—Configured individually.
Alternate function is SMOSI signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
25 23 22 17 4 16 4 P1.6/SMISO GPIO Port 1 bit 6—Configured individually.
Alternate function is SMISO signal of the SPI bus TTL
voltage thresholds. Although Vreg is not available
with the CY7C63310, 3.3V I/O is still available.
26 24 23 18
5
P1.7
GPIO Port 1 bit 7—Configured individually.
TTL voltage threshold.
7 9 9 8 13 7 11 P0.0 GPIO Port 0 bit 0—Configured individually.
On CY7C638xx and CY7C63310, external clock
input when configured as Clock In.
6 8 8 7 12 6 10 P0.1 GPIO Port 0 bit 1—Configured individually
On CY7C638xx and CY7C63310, clock output when
configured as Clock Out.
5 7 7 6 11 5 9 P0.2/INT0 GPIO port 0 bit 2—Configured individually
Optional rising edge interrupt INT0
4 6 6 5 10 4 8 P0.3/INT1 GPIO port 0 bit 3—Configured individually
Optional rising edge interrupt INT1
3 5 5 4 9 3 7 P0.4/INT2 GPIO port 0 bit 4—Configured individually
Optional rising edge interrupt INT2
Note
1. P1.0(D+) and P1.1(D-) pins must be in I/O mode when used as GPIO and in Isb mode.
Document 38-08035 Rev. *I
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