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CY7C63801 の電気的特性と機能

CY7C63801のメーカーはCypress Semiconductorです、この部品の機能は「Low-Speed USB Peripheral Controller」です。


製品の詳細 ( Datasheet PDF )

部品番号 CY7C63801
部品説明 Low-Speed USB Peripheral Controller
メーカ Cypress Semiconductor
ロゴ Cypress Semiconductor ロゴ 




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CY7C63801 Datasheet, CY7C63801 PDF,ピン配置, 機能
CY7C63310
CY7C638xx
enCoRe™ II
Low-Speed USB Peripheral Controller
1.0 Features
• enCoReTM II USB—“enhanced Component Reduction”
— Crystalless oscillator with support for an external clock.
The internal oscillator eliminates the need for an external
crystal or resonator
— Two internal 3.3V regulators and internal USB pull-up
resistor
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— Configurable IO for real-world interface without external
components
• USB Specification Compliance
— Conforms to USB Specification, Version 2.0
— Conforms to USB HID Specification, Version 1.1
— Supports one Low-Speed USB device address
— Supports one control endpoint and two data endpoints
— Integrated USB transceiver with dedicated 3.3V
regulator for USB signalling and D- pull up.
• Enhanced 8-bit microcontroller
— Harvard architecture
— M8C CPU speed can be up to 24 MHz or sourced by an
external clock signal
• Internal memory
— Up to 256 bytes of RAM
— Up to eight Kbytes of Flash including EEROM emulation
• Interface can autoconfigure to operate as PS/2 or USB
— No external components for switching between PS/2 and
USB modes
— No GPIO pins needed to manage dual-mode capability
• Low power consumption
— Typically 10 mA at 6 MHz
— 10 µA sleep
• In-system re-programmability
— Allows easy firmware update
• General purpose I/O ports
— Up to 20 General Purpose I/O (GPIO) pins
— High current drive on GPIO pins. Configurable 8- or 50-
mA/pin current sink on designated pins
— Each GPIO port supports high-impedance inputs,
configurable pull up, open drain output, CMOS/TTL
inputs, and CMOS output
— Maskable interrupts on all I/O pins
• A dedicated 3.3V regulator for the USB PHY. Aids in
signalling and D-line pull-up
• 125 mA 3.3V voltage regulator can power external 3.3V
devices
• 3.3V I/O pins
— 4 I/O pins with 3.3V logic levels
— Each 3.3V pin supports high-impedance input, internal
pull up, open drain output or traditional CMOS output
• SPI serial communication
— Master or slave operation
— Configurable up to 4 Mbit/second transfers in the master
mode
— Supports half duplex single data line mode for optical
sensors
• 2-channel 8-bit or 1-channel 16-bit capture timer registers.
Capture timer registers store both rising and falling edge
times
— Two registers each for two input pins
— Separate registers for rising and falling edge capture
— Simplifies interface to RF inputs for wireless applications
• Internal low-power wake-up timer during suspend mode
— Periodic wake-up with no external components
• 12-bit Programmable Interval Timer with interrupts
• Advanced development tools based on Cypress
MicroSystems PSoC™ tools
• Watchdog timer (WDT)
• Low-voltage detection with user-configurable threshold
voltages
• Operating voltage from 4.0V to 5.5VDC
• Operating temperature from 0–70°C
• Available in 16/18-pin PDIP, 16/18/24-pin SOIC, 24-pin
QSOP and 32-lead QFN packages
• Industry standard programmer support
1.1 Applications
The CY7C63310/CY7C638xx is targeted for the following
applications:
• PC HID devices
— Mice (optomechanical, optical, trackball)
• Gaming
— Joysticks
— Game pad
• General-purpose
— Barcode scanners
— POS terminal
— Consumer electronics
— Toys
— Remote controls
— Security dongles
Cypress Semiconductor Corporation • 198 Champion Court • San Jose, CA 95134-1709 • 408-943-2600
Document 38-08035 Rev. *I
Revised September 26, 2006
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CY7C63801 pdf, ピン配列
4.0 Logic Block Diagram
Figure 4-1. CY7C63310/CY7C638xx Block Diagram
CY7C63310
CY7C638xx
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3.3V
Regulator
Low-Speed
USB/PS2
Transceiver
and Pull-up
Low-Speed
USB SIE
Interrupt
Control
4 3VIO/SPI
Pins
Up to 14
Extended
I/O Pins
Up to 6
GPIO
pins
Wakeup
Timer
Internal
24 MHz
Oscillator
External Clock
Clock
Control
POR /
Low-Voltage
Detect
M8C CPU
Watchdog
Timer
RAM
Up to 256
Byte
Flash
Up to 8K
Byte
12-bit Timer
16-bit Free
running
timer
Document 38-08035 Rev. *I
Page 3 of 74
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CY7C63801 電子部品, 半導体
CY7C63310
CY7C638xx
Table 5-1. Pin Assignments (continued)
32
QFN
2
24
QSOP
4
24
SOIC
4
18
SIOC
3
18
PDIP
8
1 332 7
32 2 2 1 6
16
SOIC
2
1
16
PDIP
6
5
Name
Description
P0.5/TIO0 GPIO port 0 bit 5—Configured individually
Alternate function Timer capture inputs or Timer
output TIO0
P0.6/TIO1 GPIO port 0 bit 6—Configured individually
Alternate function Timer capture inputs or Timer
output TIO1
P0.7
GPIO port 0 bit 7—Configured individually
Not present in the 16 pin PDIP or SOIC package
10
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11
1
12
1
24
12
17
19
27
28
29
30
31
16 16 15 12 17 11 15
13 13 12 9 14 8 12
NC No connect
NC No connect
NC No connect
NC No connect
NC No connect
NC No connect
NC No connect
NC No connect
NC No connect
NC No connect
Vcc Supply
VSS Ground
6.0 CPU Architecture
This family of microcontrollers is based on a high performance,
8-bit, Harvard-architecture microprocessor. Five registers
control the primary operation of the CPU core. These registers
are affected by various instructions, but are not directly acces-
sible through the register space by the user.
Table 6-1. CPU Registers and Register Names
Register
Flags
Program Counter
Accumulator
Stack Pointer
Index
Register Name
CPU_F
CPU_PC
CPU_A
CPU_SP
CPU_X
The 16-bit Program Counter Register (CPU_PC) allows for
direct addressing of the full eight Kbytes of program memory
space.
The Accumulator Register (CPU_A) is the general-purpose
register that holds the results of instructions that specify any
of the source addressing modes.
The Index Register (CPU_X) holds an offset value that is used
in the indexed addressing modes. Typically, this is used to
address a block of data within the data memory space.
The Stack Pointer Register (CPU_SP) holds the address of the
current top-of-stack in the data memory space. It is affected by
the PUSH, POP, LCALL, CALL, RETI, and RET instructions,
which manage the software stack. It can also be affected by
the SWAP and ADD instructions.
The Flag Register (CPU_F) has three status bits: Zero Flag bit
[1]; Carry Flag bit [2]; Supervisory State bit [3]. The Global
Interrupt Enable bit [0] is used to globally enable or disable
interrupts. The user cannot manipulate the Supervisory State
status bit [3]. The flags are affected by arithmetic, logic, and
shift operations. The manner in which each flag is changed is
dependent upon the instruction being executed (i.e., AND,
OR, XOR). See Table 8-1.
Document 38-08035 Rev. *I
Page 6 of 74
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共有リンク

Link :


部品番号部品説明メーカ
CY7C63801

Low-Speed USB Peripheral Controller

Cypress Semiconductor
Cypress Semiconductor
CY7C63803

Low-Speed USB Peripheral Controller

Cypress Semiconductor
Cypress Semiconductor


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