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PDF ADIS16460 Data sheet ( Hoja de datos )
| Número de pieza | ADIS16460 | |
| Descripción | Six Degrees of Freedom Inertial Sensor | |
| Fabricantes | Analog Devices | |
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Data Sheet
Compact, Precision,
Six Degrees of Freedom Inertial Sensor
ADIS16460
FEATURES
GENERAL DESCRIPTION
Triaxial digital gyroscope
Measurement range: ±100°/sec (minimum)
8°/hr (typical) in-run bias stability
0.12°/√hr (typical) angle random walk, x-axis
Triaxial digital accelerometer, ±5 g dynamic range
Autonomous operation and data collection
No external configuration commands required
Fast start-up time
Factory calibrated sensitivity, bias, and axial alignment
Calibration temperature range: 0°C ≤ TA ≤ 70°C
Serial peripheral interface (SPI) data communications
Data ready signal for synchronizing data acquisition
Embedded temperature sensor
Programmable operation and control
Automatic and manual bias correction controls
Bartlett window finite impulse response (FIR) filter,
variable number of taps
External sample clock options: direct
Single command self test
Single-supply operation: 3.15 V to 3.45 V
2000 g shock survivability
Operating temperature range: −25°C to +85°C
The ADIS16460 iSensor® device is a complete inertial system
that includes a triaxial gyroscope and a triaxial accelerometer.
Each sensor in the ADIS16460 combines industry leading
iMEMS® technology with signal conditioning that optimizes
dynamic performance. The factory calibration characterizes
each sensor for sensitivity, bias, and alignment. As a result, each
sensor has its own dynamic compensation formulas that provide
accurate sensor measurements.
The ADIS16460 provides a simple, cost effective method for
integrating accurate, multiaxis inertial sensing into industrial
systems, especially when compared with the complexity and
investment associated with discrete designs. All necessary motion
testing and calibration are part of the production process at the
factory, greatly reducing system integration time. Tight orthogonal
alignment simplifies inertial frame alignment in navigation systems.
The SPI and register structures provide a simple interface for
data collection and configuration control.
The ADIS16460 is in an aluminum module package that is
approximately 22.4 mm × 22.4 mm × 9 mm and has a 14-pin
connector interface.
APPLICATIONS
Smart agriculture/construction machinery
Unmanned aerial vehicles (UAVs)/drones, and navigation
and payload stabilization
Robotics
Factory/industrial automation personnel/asset tracking
FUNCTIONAL BLOCK DIAGRAM
DR
SYNC
RST
VDD
SELF TEST
I/O
ALARMS
POWER
MANAGEMENT
GND
TRIAXIAL
GYROSCOPE
TRIAXIAL
ACCELEROMETER
TEMPERATURE
CONTROLLER
CALIBRATION
AND
FILTERS
CLOCK
ADIS16460
OUTPUT
DATA
REGISTERS
USER
CONTROL
REGISTERS
SPI
CS
SCLK
DIN
DOUT
Figure 1.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADIS16460
Data Sheet
Parameter
Logic 0 Input Current, IIL
All Pins Except RST
RST Pin
Input Capacitance, CIN
DIGITAL OUTPUTS5
Output High Voltage, VOH
Output Low Voltage, VOL
FLASH MEMORY
Data Retention7
FUNCTIONAL TIMES8
Power-On Start-Up Time
Reset Recovery Time9, 10
Reset Initiation Time11
CONVERSION RATE
x_GYRO_OUT, x_ACCL_OUT
Clock Accuracy
Sync Input Clock12
PPS Input Clock
POWER SUPPLY
Power Supply Current
Test Conditions/Comments
VIL = 0 V
ISOURCE = 1.6 mA
ISINK = 1.6 mA
Endurance6
TJ = 85°C
Time until new data is available
MSC_CTRL[3:2] = 01
MSC_CTRL[3:2] = 10
Operating voltage range, VDD
VDD = 3.15 V
Min Typ
40
1
10
2.4
10,000
20
290
222
10
2048
0.8
3.15 3.3
44
Max
60
0.4
±3
2000
128
3.45
55
Unit
µA
mA
pF
V
V
Cycles
Years
ms
ms
μs
SPS
%
Hz
Hz
V
mA
1 The X_GYRO_LOW (see Table 10), Y_GYRO_LOW (see Table 12), and Z_GYRO_LOW (see Table 14) registers capture the bit growth associated with the user
configurable filters.
2 The repeatability specifications represent analytical projections, which are based on the following drift contributions and conditions: temperature hysteresis (0°C to
70°C), electronics drift (high temperature operating life test: 85°C, 500 hours), drift from temperature cycling (JESD22, Method A104-C, Method N, 500 cycles, −40°C to
+85°C), rate random walk (10 year projection), and broadband noise.
3 Bias repeatability describes a long-term behavior, over a variety of conditions. Short-term repeatability is related to the in-run bias stability and noise density
specifications.
4 The X_ACCL_LOW (see Table 24), Y_ACCL_LOW (see Table 26), and Z_ACCL_LOW (see Table 28) registers capture the bit growth associated with the user configurable
filters.
5 The digital I/O signals are driven by an internal 3.3 V supply, and the inputs are 5 V tolerant.
6 Endurance is qualified as per JEDEC Standard 22, Method A117, and measured at −40°C, +25°C, +85°C, and +125°C.
7 The data retention lifetime equivalent is at a junction temperature (TJ) of 85°C as per JEDEC Standard 22, Method A117. Data retention lifetime decreases with junction
temperature.
8 These times do not include thermal settling and internal filter response times (375 Hz bandwidth), which may affect overall accuracy.
9 The parameter assumes that a full start-up sequence has taken place, prior to initiation of the reset cycle.
10 This parameter represents the time between raising the RST line and restoration of pulsing on the DR line, which indicates a return to normal operation.
11 This parameter represents the pulse time on the RST line, which ensures initiation of the reset operation.
12 The sync input clock functions below the specified minimum value but at reduced performance levels.
Rev. A | Page 4 of 26
5 Page 
ADIS16460
Data Sheet
THEORY OF OPERATION
The ADIS16460 is an autonomous sensor system that requires
no user initialization. When it has an adequate power supply across
the VDD and GND pins, it initializes itself and starts sampling,
processing, and loading sensor data into the output registers at a
sample rate of 2048 SPS. The DR pin (see Figure 5) pulses high
after each sample cycle concludes. The SPI interface enables simple
integration with many embedded processor platforms, as shown
in Figure 17 (electrical connection) and Table 6 (pin functions).
I/O LINES ARE COMPATIBLE WITH
VDD
3.3V LOGIC LEVELS
+3.3V
SYSTEM
PROCESSOR
SPI MASTER
SS
SCLK
MOSI
MISO
IRQ
11
6 CS ADIS16460
3 SCLK
5 DIN
4 DOUT
1 DR
13
Figure 17. Electrical Connection Diagram
Table 6. Generic Master Processor Pin Names and Functions
Pin Name
Function
SS Slave select
SCLK
Serial clock
MOSI
Master output, slave input
MISO
Master input, slave output
IRQ Interrupt request
The ADIS16460 SPI interface supports full duplex serial commu-
nication (simultaneous transmit and receive) and uses the bit
sequence shown in Figure 20. Table 7 provides a list of the most
common settings that require attention to initialize the serial
port of a processor for the ADIS16460.
Table 7. Generic Master Processor SPI Settings
Processor Setting Description
Master
The ADIS16460 operates as a slave
SCLK Rate1
Maximum serial clock rate, see Table 2
SPI Mode 3
CPOL = 1 (polarity), CPHA = 1 (phase)
MSB First
Bit sequence, see Figure 20
16-Bit Length
Shift register/data length
1 For burst read, SCLK rate ≤ 1 MHz.
READING SENSOR DATA
The ADIS16460 provides two options for acquiring sensor data:
a single register and a burst register. A single register read requires
two 16-bit SPI cycles. The first cycle requests the contents of a
register using the bit assignments in Figure 20. Bit DC7 to Bit DC0
are don’t cares for a read, and then the output register contents
follow on DOUT during the second sequence. Figure 18 includes
three single register reads in succession.
In this example, the process starts with DIN = 0x0600 to request
the contents of X_GYRO_OUT, then follows with 0x0A00 to
request Y_GYRO_OUT, and 0x0E00 to request Z_GYRO_OUT.
Full duplex operation enables processors to use the same 16-bit
SPI cycle to read data from DOUT while requesting the next set
of data on DIN. Figure 19 provides an example of the four SPI
signals when reading X_GYRO_OUT in a repeating pattern.
DIN 0x0600
0x0A00
0x0E00
DOUT
X_GYRO_OUT Y_GYRO_OUT Z_GYRO_OUT
Figure 18. SPI Read Example
CS
SCLK
DIN DIN = 0000 0110 0000 0000 = 0x0600
DOUT
DOUT = 1111 1111 1111 1010 = 0xFFFA = –6 LSB = –0.03°/sec
Figure 19. Example SPI Read, Second Sequence
CS
SCLK
DIN R/W A6 A5 A4 A3 A2 A1 A0 DC7 DC6 DC5 DC4 DC3 DC2 DC1 DC0
DOUT
D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
NOTES
1. THE DOUT BIT PATTERN REFLECTS THE ENTIRE CONTENTS OF THE REGISTER IDENTIFIED BY [A6:A0]
IN THE PREVIOUS 16-BIT DIN SEQUENCE WHEN R/W = 0.
2. IF R/W = 1 DURING THE PREVIOUS SEQUENCE, DOUT IS NOT DEFINED.
Figure 20. SPI Communication Bit Sequence
R/W A6 A5
D15 D14 D13
Rev. A | Page 10 of 26
11 Page | ||
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