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PDF ADP5073 Data sheet ( Hoja de datos )
| Número de pieza | ADP5073 | |
| Descripción | DC-to-DC Inverting Regulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Data Sheet
1.2 A, DC-to-DC Inverting Regulator
ADP5073
FEATURES
Wide input voltage range: 2.85 V to 15 V
Adjustable negative output to VIN − 39 V
Integrated 1.2 A main switch
1.2 MHz/2.4 MHz switching frequency with optional external
frequency synchronization from 1.0 MHz to 2.6 MHz
Resistor programmable soft start timer
Slew rate control for lower system noise
Precision enable control
Power-good output
UVLO, OCP, OVP, and TSD protection
3 mm × 3 mm, 16-lead LFCSP
−40°C to +125°C junction temperature
Supported by the ADIsimPower tool set
APPLICATIONS
Bipolar amplifiers, ADCs, digital-to-analog converters
(DACs), and multiplexers
High speed converters
Radio frequency (RF) power amplifier (PA) bias
Optical modules
TYPICAL APPLICATION CIRCUIT
VIN
CIN
ON
OFF
CVREG
AVIN
PVIN
VREF
ADP5073 FB
EN
VREG
SW
RPG
SS
PWRGD
CC
PWRGD
SLEW
COMP SYNC/FREQ
RC GND
CVREF
RFB
RFT
D1
L1
VOUT
COUT
Figure 1.
GENERAL DESCRIPTION
The ADP5073 is a high performance dc-to-dc inverting regulator
used to generate negative supply rails.
The input voltage range of 2.85 V to 15 V supports a wide variety of
applications. The integrated main switch enables the generation of
an adjustable negative output voltage down to 39 V below the
input voltage.
The ADP5073 operates at a pin selected 1.2 MHz/2.4 MHz
switching frequency. The ADP5073 can synchronize with an
external oscillator from 1.0 MHz to 2.6 MHz to ease noise
filtering in sensitive applications. The regulator implements
programmable slew rate control circuitry for the MOSFET
driver stage to reduce electromagnetic interference (EMI).
The ADP5073 includes a fixed internal or resistor programmable
soft start timer to prevent inrush current at power-up. During
shutdown, the regulator completely disconnects the load from the
input supply to provide a true shutdown. A power-good pin is
available to indicate the output is stable.
Other key safety features in the ADP5073 include overcurrent
protection (OCP), overvoltage protection (OVP), thermal
shutdown (TSD), and input undervoltage lockout (UVLO).
The ADP5073 is available in a 16-lead LFCSP and is rated for a
−40°C to +125°C operating junction temperature range.
Table 1. Related Devices
Device
Boost
Switch (A)
ADP5070 1.0
Inverter
Switch (A)
0.6
ADP5071 2.0
1.2
ADP5073
ADP5074
ADP5075
Not
applicable
Not
applicable
Not
applicable
1.2
2.4
0.8
Package
20-lead LFCSP (4 mm ×
4 mm) and TSSOP
20-lead LFCSP (4 mm ×
4 mm) and TSSOP
16-lead LFCSP (3 mm ×
3 mm)
16-lead LFCSP (3 mm ×
3 mm)
12-ball WLCSP
(1.61 mm × 2.18 mm)
Rev. 0
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP5073
Parameter
Error Amplifier (EA) Transconductance
Power FET On Resistance
Power FET Maximum Drain Source Voltage
Current-Limit Threshold
Minimum On Time
Minimum Off Time
SOFT START
Soft Start Timer
Symbol
gM
RDS (ON)
VDS (MAX)
ILIM
tSS
Hiccup Time
THERMAL SHUTDOWN
Threshold
Hysteresis
tHICCUP
TSHDN
THYS
Data Sheet
Min Typ Max Unit Test Conditions/Comments
270 300 330 µA/V
200 mΩ VIN = 5 V
39 V
1.2 1.375 1.6 A
55 ns
50 ns
4
32
8 × tSS
ms SS = open
ms SS resistor = 50 kΩ to GND
ms
150 °C
15 °C
Rev. 0 | Page 4 of 17
5 Page 
ADP5073
Data Sheet
THEORY OF OPERATION
VIN
CIN
SYNC/
FREQ
AVIN
VREG
CVREG
PVIN
SLEW
VREG EN
(OPTRIPOGNAL)
PWRGD
HIGH VOLTAGE
REGULATOR
EN
HIGH VOLTAGE
BAND GAP
PLL
OSCILLATOR
CURRENT
SENSE
INVERTER
PWM CONTROL
SLEW
ERROR AMP
REF
SW D1
L1 COUT
RFT
FB
CONTROL
REF
FB
THERMAL
SHUTDOWN
POWER
GOOD
UVLO
OVP
VREG
4µA
REF_1.6V VREF
COMP
START-UP REFERENCE REF
TIMERS GENERATOR REF_1.6V
RC
SS
RSS (OPTIONAL)
GND
CC
RFB
CVREF
Figure 21. Functional Block Diagram
PWM MODE
OSCILLATOR AND SYNCHRONIZATION
The inverting regulator in the ADP5073 operates at a fixed fre-
quency set by an internal oscillator. At the start of each oscillator
cycle, the MOSFET switch turns on, applying a positive voltage
across the inductor. The inductor current (IINDUCTOR) increases
until the current sense signal crosses the peak inductor current
threshold that turns off the MOSFET switch; this threshold is set
by the error amplifier output. During the MOSFET off time, the
inductor current declines through the external diode until the next
oscillator clock pulse starts a new cycle. The ADP5073 regulates the
output voltage by adjusting the peak inductor current threshold.
SKIP MODE
During light load operation, the regulator can skip pulses to
maintain output voltage regulation. Skipping pulses increases
the device efficiency. The COMP voltage is monitored internally
and when it falls below a threshold (due to the output voltage
rising above the target during a switching cycle), the next switching
cycle is skipped. This voltage is monitored on a cycle-by-cycle
basis. During skip operation, the output ripple is increased and
the ripple frequency varies. The choice of inductor defines the
output current below which skip mode occurs.
UNDERVOLTAGE LOCKOUT (UVLO)
The UVLO circuitry monitors the AVIN pin voltage level. If the
input voltage drops below the VUVLO_FALLING threshold, the
regulator turns off. After the AVIN pin voltage rises above the
VUVLO_RISING threshold, the soft start period initiates, and the
regulator is enabled.
A phase-locked loop (PLL)-based oscillator generates the internal
clock and offers a choice of two internally generated frequency
options or external clock synchronization. The switching frequency
is configured using the SYNC/FREQ pin options shown in Table 6.
For external synchronization, connect the SYNC/FREQ pin to a
suitable clock source. The PLL locks to an input clock within
the range specified by fSYNC.
Table 6. SYNC/FREQ Pin Options
SYNC/FREQ Pin Switching Frequency
High
2.4 MHz
Low 1.2 MHz
External Clock
1× clock frequency
INTERNAL REGULATORS
The internal VREG regulator in the ADP5073 provides a stable
power supply for the internal circuitry. The VREG supply provides
a high signal for device configuration pins but must not be used
to supply external circuitry.
The VREF regulator provides a reference voltage for the inverting
regulator feedback network to ensure a positive feedback voltage
on the FB pin. A current-limit circuit is included for both internal
regulators to protect the circuit from accidental loading.
Rev. 0 | Page 10 of 17
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet ADP5073.PDF ] | |
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