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ADP121 の電気的特性と機能

ADP121のメーカーはAnalog Devicesです、この部品の機能は「CMOS Linear Regulator」です。


製品の詳細 ( Datasheet PDF )

部品番号 ADP121
部品説明 CMOS Linear Regulator
メーカ Analog Devices
ロゴ Analog Devices ロゴ 




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ADP121 Datasheet, ADP121 PDF,ピン配置, 機能
Data Sheet
FEATURES
Input voltage range: 2.3 V to 5.5 V
Output voltage range: 1.2 V to 3.3 V
Output current: 150 mA
Low quiescent current
IGND = 11 μA with 0 μA load
IGND = 30 μA with 150 mA load
Low shutdown current: <1 μA
Low dropout voltage
90 mV @ 150 mA load
High PSRR
70 dB @ 1 kHz at VOUT = 1.2 V
70 dB @ 10 kHz at VOUT = 1.2 V
Low noise: 40 μV rms at VOUT = 1.2 V
No noise bypass capacitor required
Output voltage accuracy: ±1%
Stable with a small 1 μF ceramic output capacitor
Current limit and thermal overload protection
Logic controlled enable
5-lead TSOT package
4-ball 0.4 mm pitch WLCSP
APPLICATIONS
Mobile phones
Digital cameras and audio devices
Portable and battery-powered equipment
Post dc-to-dc regulation
Post regulation
GENERAL DESCRIPTION
The ADP121 is a quiescent current, low dropout, linear regulator
that operates from 2.3 V to 5.5 V and provides up to 150 mA of
output current. The low 135 mV dropout voltage at 150 mA
load improves efficiency and allows operation over a wide
input voltage range. The low 30 μA of quiescent current at full
load makes the ADP121 ideal for battery-operated portable
equipment.
150 mA, Low Quiescent Current,
CMOS Linear Regulator
ADP121
TYPICAL APPLICATION CIRCUITS
VIN = 2.3V
CIN
1µF
1 VIN VOUT 5
VOUT = 1.8V
2 GND
COUT
1µF
ON 3 EN
NC 4
OFF
NC = NO CONNECT
Figure 1. ADP121 TSOT with Fixed Output Voltage, 1.8 V
VIN = 2.3V
CIN
1µF
VOUT = 1.8V
VIN VOUT
COUT
1µF
ON
OFF
EN
GND
Figure 2. ADP121 WLCSP with Fixed Output Voltage, 1.8 V
The ADP121 is available in output voltages ranging from 1.2 V
to 3.3 V. The parts are optimized for stable operation with small
1 μF ceramic output capacitors. The ADP121 delivers good
transient performance with minimal board area.
Short-circuit protection and thermal overload protection circuits
prevent damage in adverse conditions. The ADP121 is available
in a tiny 5-lead TSOT and 4-ball 0.4 mm pitch halide-free
WLCSP packages and utilizes the smallest footprint solution to
meet a variety of portable applications.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2008–2012 Analog Devices, Inc. All rights reserved.

1 Page





ADP121 pdf, ピン配列
ADP121
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications....................................................................................... 1
Typical Application Circuits............................................................ 1
General Description ......................................................................... 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Recommended Specifications: Input and Output Capacitors 4
Absolute Maximum Ratings............................................................ 5
Thermal Data ................................................................................ 5
Thermal Resistance ...................................................................... 5
ESD Caution.................................................................................. 5
Pin Configurations and Function Descriptions ........................... 6
REVISION HISTORY
8/12—Rev. F to Rev. G
Change to Ordering Guide.............................................................19
7/12—Rev. E to Rev. F
Updated Outline Dimensions ........................................................18
Change to Ordering Guide.............................................................19
8/11—Rev. D to Rev. E
Changes to Figure 22........................................................................ 9
Changes to Ordering Guide .......................................................... 19
1/10—Rev. C to Rev. D
Changes to Ordering Guide .......................................................... 19
11/09—Rev. B to Rev. C
Changes to Figure 1, Figure 2, and General Description
Section................................................................................................ 1
Data Sheet
Typical Performance Characteristics ..............................................7
Theory of Operation ...................................................................... 11
Applications Information .............................................................. 12
Capacitor Selection .................................................................... 12
Undervoltage Lockout ............................................................... 13
Enable Feature ............................................................................ 13
Current Limit and Thermal Overload Protection ................. 14
Thermal Considerations............................................................ 14
PCB Layout Considerations...................................................... 17
Outline Dimensions ....................................................................... 18
Ordering Guide .......................................................................... 19
Changes to Table 3.............................................................................5
Changes to Figure 46 Caption and Figure 47 Caption .............. 17
Changes to Ordering Guide .......................................................... 19
9/09—Rev. A to Rev. B
Updated Outline Dimensions....................................................... 18
Changes to Ordering Guide .......................................................... 19
3/09—Rev. 0 to Rev. A
Changes to Features and General Description Sections ..............1
Changes to Input and Output Capacitor Parameter.....................4
Changes to Figure 17 to Figure 20...................................................9
Changes to Figure 49...................................................................... 17
Added Figure 50 ............................................................................. 17
Changes to Ordering Guide .......................................................... 19
7/08—Revision 0: Initial Version
Rev. G | Page 2 of 20


3Pages


ADP121 電子部品, 半導体
Data Sheet
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter
VIN to GND
VOUT to GND
EN to GND
Storage Temperature Range
Operating Junction Temperature Range
Soldering Conditions
Rating
−0.3 V to +6.5 V
−0.3 V to VIN
−0.3 V to +6.5 V
−65°C to +150°C
−40°C to +125°C
JEDEC J-STD-020
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
THERMAL DATA
Absolute maximum ratings apply individually only, not in
combination. The ADP121 can be damaged when the junction
temperature limits are exceeded. Monitoring the ambient
temperature does not guarantee that the junction temperature
(TJ) is within the specified temperature limits. In applications
with high power dissipation and poor thermal resistance, the
maximum ambient temperature may have to be derated.
In applications with moderate power dissipation and low PCB
thermal resistance, the maximum ambient temperature can
exceed the maximum limit as long as the junction temperature
is within specification limits. TJ of the device is dependent on
the ambient temperature (TA), the power dissipation of the
device (PD), and the junction-to-ambient thermal resistance of
the package (θJA). TJ is calculated from TA and PD using the
following formula:
TJ = TA + (PD × θJA)
ADP121
Junction-to-ambient thermal resistance, θJA, is based on
modeling and calculation using a four-layer board. The
junction-to-ambient thermal resistance is highly dependent
on the application and board layout. In applications where high
maximum power dissipation exists, close attention to thermal
board design is required. The value of θJA may vary, depending
on PCB material, layout, and environmental conditions. The
specified values of θJA are based on a 4-layer, 4” × 3”, circuit
board. Refer to JESD 51-7 and JESD 51-9 for detailed
information on the board construction. For additional
information, see AN-617 Application Note, MicroCSPTM
Wafer Level Chip Scale Package.
ΨJB is the junction-to-board thermal characterization parameter
measured in °C/W. ΨJB is based on modeling and calculation
using a four-layer board. The JESD51-12 Guidelines for Reporting
and Using Package Thermal Information states that thermal
characterization parameters are not the same as thermal
resistances. ΨJB measures the component power flowing
through multiple thermal paths rather than a single path as in
thermal resistance, θJB. Therefore, ΨJB thermal paths include
convection from the top of the package as well as radiation
from the package, factors that make ΨJB more useful in real-
world applications. Maximum TJ is calculated from the board
temperature (TB) and PD using the following formula:
TJ = TB + (PD × ΨJB)
Refer to JESD51-8 and JESD51-12 for more detailed
information about ΨJB.
THERMAL RESISTANCE
θJA and ΨJB are specified for the worst-case conditions, that is, a
device soldered in a circuit board for surface-mount packages.
Table 4. Thermal Resistance
Package Type
5-Lead TSOT
4-Ball 0.4 mm Pitch WLCSP
θJA ΨJB Unit
170 43 °C/W
260 58 °C/W
ESD CAUTION
Rev. G | Page 5 of 20

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共有リンク

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