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PDF ADP7112 Data sheet ( Hoja de datos )
| Número de pieza | ADP7112 | |
| Descripción | CMOS LDO Linear Regulator | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de ADP7112 (archivo pdf) en la parte inferior de esta página. Total 22 Páginas | ||
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Data Sheet
FEATURES
Low noise: 11 µV rms independent of fixed output voltage
PSRR of 88 dB at 10 kHz, 68 dB at 100 kHz, 50 dB at 1 MHz,
VOUT = 5 V, VIN = 7 V
Input voltage range: 2.7 V to 20 V
Maximum output current: 200 mA
Initial accuracy: ±0.8%
Accuracy over line, load, and temperature
±1.8%, TJ = −40°C to +125°C
Low dropout voltage: 200 mV (typical) at a 200 mA load,
VOUT = 5 V
User-programmable soft start
Low quiescent current, IGND = 50 μA (typical) with no load
Low shutdown current
1.8 μA at VIN = 5 V
3.0 μA at VIN = 20 V
Stable with a small 2.2 µF ceramic output capacitor
Fixed output voltage options: 1.8 V, 2.5 V, 3.3 V, and 5.0 V
15 standard voltages between 1.2 V and 5.0 V are available
Adjustable output from 1.2 V to VIN – VDO, output can be
adjusted above initial set point
Precision enable
1 mm × 1.2 mm, 6-ball WLCSP
APPLICATIONS
Regulation to noise sensitive applications
ADC and DAC circuits, precision amplifiers, power for
VCO VTUNE control
Communications and infrastructure
Medical and healthcare
Industrial and instrumentation
GENERAL DESCRIPTION
The ADP7112 is a CMOS, low dropout (LDO) linear regulator
that operates from 2.7 V to 20 V and provides up to 200 mA of
output current. This high input voltage LDO is ideal for the
regulation of high performance analog and mixed-signal circuits
operating from 20 V down to 1.2 V rails. Using an advanced
proprietary architecture, the device provides high power supply
rejection, low noise, and achieves excellent line and load transient
response with a small 2.2 µF ceramic output capacitor. The
ADP7112 regulator output noise is 11 μV rms, independent of
the output voltage for the fixed options of 5 V or less.
20 V, 200 mA, Low Noise,
CMOS LDO Linear Regulator
ADP7112
TYPICAL APPLICATION CIRCUITS
VIN = 6V
CIN
2.2µF
ON
OFF
ADP7112
VIN VOUT
SENSE/ADJ
EN SS
GND
VOUT = 5V
COUT
2.2µF
CSS
1nF
Figure 1. ADP7112 with Fixed Output Voltage, 5 V
VIN = 7V
CIN
2.2µF
ON
OFF
ADP7112
VIN VOUT
SENSE/ADJ
EN SS
GND
VOUT = 6V
2kΩ
COUT
2.2µF
10kΩ
CSS
1nF
Figure 2. ADP7112 with 5 V Output Adjusted to 6 V
The ADP7112 is available in 15 fixed output voltage options.
The following voltages are available from stock: 1.2 V (adjustable),
1.8 V, 2.5 V, 3.3 V, and 5.0 V. Additional voltages available by
special order are 1.5 V, 1.85 V, 2.0 V, 2.2 V, 2.75 V, 2.8 V, 2.85 V,
3.8 V, 4.2 V, and 4.6 V.
Each fixed output voltage can be adjusted above the initial set
point with an external feedback divider. This allows the ADP7112
to provide an output voltage from 1.2 V to VIN − VDO with high
PSRR and low noise.
A user-programmable soft start with an external capacitor is
available in the ADP7112. The ADP7112 is available in a 6-ball
1 mm × 1.2 mm WLCSP, making it a very compact solution.
Rev. C
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2014–2016 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP7112
Data Sheet
INPUT AND OUTPUT CAPACITANCE, RECOMMENDED SPECIFICATIONS
Table 2.
Parameter
INPUT AND OUTPUT CAPACITANCE
Minimum Capacitance1
Capacitor Effective Series Resistance (ESR)
Symbol Test Conditions/Comments
CMIN TA = −40°C to +125°C
RESR TA = −40°C to +125°C
Min Typ Max Unit
1.5
0.001
µF
0.3 Ω
1 The minimum input and output capacitance must be greater than 1.5 μF over the full range of operating conditions. The full range of operating conditions in the
application must be considered during device selection to ensure that the minimum capacitance specification is met. X7R and X5R type capacitors are recommended,
whereas Y5V and Z5U capacitors are not recommended for use with any LDO.
Rev. C | Page 4 of 21
5 Page 
ADP7112
700
LOAD = 5mA
LOAD = 10mA
600 LOAD = 50mA
LOAD = 100mA
LOAD = 150mA
500 LOAD = 200mA
400
300
200
100
0
3.1 3.3 3.5 3.7 3.9
VIN (V)
Figure 22. Ground Current vs. Input Voltage (VIN) in Dropout, VOUT = 3.3 V
300
VIN = 2.7V
VIN = 5.0V
250
VIN = 10V
VIN = 20V
200
150
100
50
0
–40
–5 25 85
TEMPERATURE (°C)
125
Figure 23. Soft Start (SS) Current vs. Temperature, Multiple Input Voltages,
VOUT = 5 V
0
3.0V
–10
2.0V
1.6V
1.4V
–20 1.2V
1.0V
–30 800mV
700mV
–40 600mV
–50
–60
–70
–80
–90
–100
1
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 24. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 1.8 V,
for Various Headroom Voltages
Data Sheet
0
–10
–20
–30
–40
–50
–60
10Hz
–70 100Hz
1kHz
–80 10kHz
100kHz
–90 1MHz
–100
10MHz
0.2 0.6 1.0 1.4 1.8 2.2 2.6 3.0
HEADROOM VOLTAGE (V)
Figure 25. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = 1.8 V, for Different Frequencies
0
–20
–40
–60
–80
–100
3.0V
2.0V
1.6V
1.4V
1.2V
1.0V
800mV
700mV
600mV
–120
500mV
10 100 1k 10k 100k 1M 10M
FREQUENCY (Hz)
Figure 26. Power Supply Rejection Ratio (PSRR) vs. Frequency, VOUT = 3.3 V,
for Various Headroom Voltages
0
10Hz
–10
100Hz
1kHz
10kHz
–20 100kHz
1MHz
–30 10MHz
–40
–50
–60
–70
–80
–90
–100
0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2 2.4 2.6 2.8 3.0
HEADROOM VOLTAGE (V)
Figure 27. Power Supply Rejection Ratio (PSRR) vs. Headroom Voltage,
VOUT = 3.3 V, for Different Frequencies
Rev. C | Page 10 of 21
11 Page | ||
| Páginas | Total 22 Páginas | |
| PDF Descargar | [ Datasheet ADP7112.PDF ] | |
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