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PDF ADP5062 Data sheet ( Hoja de datos )
| Número de pieza | ADP5062 | |
| Descripción | Linear Li-Ion Battery Charger | |
| Fabricantes | Analog Devices | |
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Data Sheet
Linear Li-Ion Battery Charger with Power
Path and USB Compatibility in LFCSP
ADP5062
FEATURES
4 mm × 4 mm LFCSP package
Fully programmable via I2C
Flexible digital control inputs
Up to 2.1 A current from an ac charger in LDO mode
Operating input voltage from 4.0 V to 6.7 V
Tolerant input voltage from −0.5 V to +20 V (USB VBUS)
Fully compatible with USB 3.0 and USB Battery Charging
Specification 1.2
Built-in current sensing and limiting
As low as 54 mΩ battery isolation FET between battery and
charger output
Thermal regulation prevents overheating
Compliant with JEITA 1 and JEITA 2 Li-Ion battery charging
temperature specifications
SYS_EN flag permits the system to be disabled until battery is at
the minimum required level for guaranteed system start-up
APPLICATIONS
Digital still cameras
Digital video cameras
Single cell Li-Ion portable equipment
PDAs, audio, and GPS devices
Portable medical devices
Mobile phones
GENERAL DESCRIPTION
The ADP5062 charger is fully compliant with USB 3.0 and the
USB Battery Charging Specification 1.2 and enables charging
via the mini USB VBUS pin from a wall charger, car charger, or
USB host port.
The ADP5062 operates from a 4 V to 6.7 V input voltage range
but is tolerant of voltages up to 20 V thereby alleviating concerns
about USB bus spikes during disconnect or connect scenarios.
The ADP5062 features an internal FET between the linear
charger output and the battery. This permits battery isolation
and, hence, system powering under a dead battery or no battery
scenario, which allows for immediate system function on connec-
tion to a USB power supply.
Based on the type of USB source, which is detected by an external
USB detection chip, the ADP5062 can be set to apply the correct
current limit for optimal charging and USB compliance.
The ADP5062 has three factory-programmable digital input/out-
put pins that provide maximum flexibility for different systems.
These digital input/output pins permit combinations of features
such as, input current limits, charging enable and disable, charging
current limits, and a dedicated interrupt output pin.
TYPICAL APPLICATION CIRCUIT
AC OR
USB
VBUS
C4
10µF
VIN
CBP
C1
10nF
ADP5062
ISO_Sx SYSTEM
C3
22µF
SCL
SDA
DIG_IO1
DIG_IO2
DIG_IO3
SYS_EN
CHARGER
CONTROL
BLOCK
AGND
Figure 1.
ISO_Bx
BAT_SNS
+ Li-ion
THR
C2
22µF
ILED
VLED
Rev. B
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2012–2013 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com
1 page  
ADP5062
Parameter
BATTERY ISOLATION FET
Pin to Pin Resistance Between ISO_Sx
and ISO_Bx
Regulated System Voltage: VBAT Low
Battery Supplementary Threshold
LDO AND HIGH VOLTAGE BLOCKING
Regulated System Voltage
Load Regulation
High Voltage Blocking FET (LDO FET)
On Resistance
Maximum Output Current
VINx Input Voltage, Good Threshold
Rising
VINx Falling
VINx Input Overvoltage Threshold
Hysteresis
VINx Transition Timing
THERMAL CONTROL
Isothermal Charging Temperature
Thermal Early Warning Temperature
Thermal Shutdown Temperature
THERMISTOR CONTROL
Thermistor Current
10,000 NTC
100,000 NTC
Thermistor Capacitance
Cold Temperature Threshold
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
Hot Temperature Threshold
Resistance Thresholds
Hot to Typical Resistance
Typical to Hot Resistance
JEITA1 Li-ION BATTERY CHARGING
SPECIFICATION DEFAULTS5
JEITA Cold Temperature
Resistance Thresholds
Cool to Cold Resistance
Cold to Cool Resistance
JEITA Cool Temperature
Resistance Thresholds
Typical to Cool Resistance
Cool to Typical Resistance
JEITA Warm Temperature
Resistance Thresholds
Warm to Typical Resistance
Typical to Warm Resistance
Symbol Min
RDSON_ISO
VISO_SFC
VTHISO
3.6
3.2
0
VISO_STRK
4.214
RDS(ON)HV
VVIN_OK_RISE 3.75
VVIN_OK_FALL
VVIN_OV
ΔVVIN_OV
TVIN_RISE
TVIN_FALL
6.7
10
10
TLIM
TSDL
TSD
Typ
54
3.8
3.4
5
4.3
−0.56
330
2.1
3.9
3.6
6.9
0.1
115
130
140
110
INTC_10k
INTC_100k
CNTC
TNTC_COLD
100
0
RCOLD_FALL
RCOLD_RISE
TNTC_HOT
20,500
25,600
24,400
60
RHOT_FALL
RHOT_RISE
2750
3700
3350
TJEITA_COLD
0
RCOLD_FALL
RCOLD_RISE
TJEITA_COOL
20,500
25,600
24,400
10
RTYP_FALL
RTYP_RISE
TJEITA_WARM
13,200
16,500
15,900
45
RWARM_FALL
RWARM_RISE
4260
5800
5200
Data Sheet
Max
89
4.0
3.5
12
4.386
485
4.0
3.7
7.2
Unit Test Conditions/Comments
mΩ On battery supplement mode, VINx = 0 V, VISO_Bx =
4.2 V, IISO_Bx = 500 mA
V VTRM[5:0] programming ≥ 4.00 V
V VTRM[5:0] programming < 4.00 V
mV VISO_Sx < VISO_Bx, VSYS rising
V VSYSTEM[2:0] = 000 (binary) = 4.3 V, IISO_Sx =
100 mA, LDO mode2
%/A IISO_Sx = 0 m A to 1500 mA
mΩ IVINx = 500 mA
A VISO_Sx = 4.3 V, LDO mode
V
V
V
V
µs Minimum rise time for VINx from 5 V to 20 V
µs Minimum fall time for VINx from 4 V to 0 V
°C
°C
°C TJ rising
°C TJ falling
400 μA
40 μA
pF
°C
30,720
Ω
Ω
°C
3950
Ω
Ω
No battery charging occurs
No battery charging occurs
°C
30,720
Ω
Ω
°C
19,800
Ω
Ω
°C
6140
Ω
Ω
No battery charging occurs
Battery charging occurs at 50% of programmed
level
Battery termination voltage (VTRM) is reduced by
100 mV
Rev. B | Page 4 of 44
5 Page 
ADP5062
Data Sheet
TYPICAL PERFORMANCE CHARACTERISTICS
VVINx = 5.0 V, CVINx = 10 µF, CISO_Sx = 44 µF, CISO_Bx = 22 µF, CCBP = 10 nF, all registers at default values, unless otherwise noted.
4.40 5.10
4.38 5.08
4.36 5.06
4.34 5.04
4.32 5.02
4.30 5.00
4.28 4.98
4.26 4.96
4.24 4.94
4.22 4.92
4.20
0.01
0.1
1
SYSTEM OUTPUT CURRENT (A)
Figure 4. System Voltage vs. System Output Current, LDO Mode,
VSYSTEM[2:0] = 000 (Binary) = 4.3 V
4.90
0.01
0.1
1
SYSTEM OUTPUT CURRENT (A)
Figure 7. System Voltage vs. System Output Current, LDO Mode, VVINx = 6.0 V,
VSYSTEM[2:0] = 111 (Binary) = 5.0 V
4.5
LOAD = 100mA
4.4
LOAD = 500mA
LOAD = 1000mA
4.3
4.2
4.1
4.0
3.9
3.8
3.7
3.6
3.5
4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8
INPUT VOLTAGE (V)
Figure 5. System Voltage vs. Input Voltage (in Dropout), LDO Mode,
VSYSTEM[2:0] = 000 (Binary) = 4.3 V
5.4
LOAD = 100mA
5.2
LOAD = 500mA
LOAD = 1000mA
5.0
4.8
4.6
4.4
4.2
4.0
3.8
3.6
3.4
4.0 4.4 4.8 5.2 5.6 6.0 6.4 6.8
INPUT VOLTAGE (V)
Figure 8. System Voltage vs. Input Voltage (in Dropout), LDO Mode,
VSYSTEM[2:0] = 111 (Binary) = 5.0 V
1000
900
800
700 LIMIT = 900mA
LIMIT = 500mA
600 LIMIT = 100mA
500
400
300
200
100
0
2.7 3.2 3.7 4.2
BATTERY VOLTAGE (V)
Figure 6. Input Current-Limited Charge Current vs. Battery Voltage
700
600
WEAK
CHARGE
500
FAST CHARGE
400
300
200
TRICKLE CHARGE
100
0
2.3 2.8 3.3 3.8 4.3
BATTERY VOLTAGE (V)
Figure 9. Battery Charge Current vs. Battery Voltage, ICHG[4:0] = 01001
(Binary) = 500 mA, ILIM[3:0] = 1111 (Binary) = 2100 mA
Rev. B | Page 10 of 44
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet ADP5062.PDF ] | |
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